Copper Plating on Glass Using a Solution Processed Copper-Titanium Oxide Catalytic Adhesion Layer

2016 ◽  
Vol 163 (5) ◽  
pp. D201-D205 ◽  
Author(s):  
Kyohei Okabe ◽  
Takahiro Kagami ◽  
Yoshio Horiuchi ◽  
Osamu Takai ◽  
Hideo Honma ◽  
...  
2017 ◽  
Vol 2017 (1) ◽  
pp. 000458-000463
Author(s):  
Michael Merschky ◽  
Fabian Michalik ◽  
Martin Thoms ◽  
Robin Taylor ◽  
Diego Reinoso-Cocina ◽  
...  

Abstract With the trends towards miniaturization and heterogeneous integration, both IC and advanced substrate manufacturers are striving to meet the needs of next generation platforms, to increase the density of interconnects, and generate conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and Advanced Modified-Semi-Additive-Processing (amSAP) were devised, realized and implemented in order to meet these requirements. Line and space (L/S) requirements of copper conductors will be below 5/5μm for advanced substrates, with 2/2μm L/S required for chip to chip connections in the near future. Herein we report about the performance of the new developed ferric sulfate based EcoFlash™ process for SAP and amSAP application with the focus on glass as the substrate and VitroCoat as thin metal oxide adhesion promotion layer. The adhesion promotion layer (about 5–10 nm thickness) is dip-coated by a modified sol-gel process followed by sintering which creates chemical bonds to the glass. The sol-gel dip coating process offers good coating uniformity on both Though-Glass-Via (TGV) and glass surfaces under optimized coating conditions. Uniform coating can be achieved up to aspect ratios of 10:1 by using a 300μm thick glass with 30μm diameter TGV. The thin adhesive layer enables electroless and electrolytic copper plating directly onto glass substrates. Excellent adhesion of electroless plated copper seed layer on glass can be achieved by using the adhesive layer and annealing technology. The thin adhesive layer is non-conductive and can be easily removed from the area between circuit traces together with the electroless copper seed layer by etching with a ferric sulfate based process. We have successfully integrated the adhesion layer and electroless and electrolytic copper plating technologies into semi-additive process and seed layer etching capable producing L/S below 10 μm.


2009 ◽  
Vol 19 (14) ◽  
pp. 2082 ◽  
Author(s):  
Junggwon Yun ◽  
Kyoungah Cho ◽  
Byoungjun Park ◽  
Bae Ho Park ◽  
Sangsig Kim

2019 ◽  
Vol 11 (16) ◽  
pp. 14840-14847 ◽  
Author(s):  
Joo Sung Kim ◽  
Sung Woon Cho ◽  
Nishad G. Deshpande ◽  
Young Been Kim ◽  
Young Dae Yun ◽  
...  

1995 ◽  
Vol 10 (6) ◽  
pp. 1508-1515 ◽  
Author(s):  
G.R. Fox ◽  
S. Trolier-McKinstry ◽  
S.B. Krupanidhi ◽  
L.M. Casas

Pt/Ti/SiO2/Si structures have been studied to investigate the structural, chemical, and microstructural changes that occur during annealing. Grain growth of the as-deposited Pt columns was observed after annealing at 650 °C, and extensive changes in the Pt microstructure were apparent following a 750 °C anneal for 20 min. In addition, two types of defects were identified on the surfaces of annealed substrates. Defect formation was retarded when the surface was covered with a ferroelectric film. Concurrent with the annealing-induced Pt microstructure changes, Ti from the adhesion layer between the Pt and the SiO2 migrated into the Pt layer and oxidized. It was shown with spectroscopic ellipsometry and Auger electron spectroscopy that for long annealing times, the titanium oxide layer can reach the Pt surface. Consequently, at the processing temperatures utilized in preparing many ferroelectric thin films, the substrate is not completely inert or immobile. The changes associated with Ti migration could be especially problematic in techniques that require the substrate to be heated prior to film deposition.


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