Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometer Focal Plane Arrays

Adriana Lapadatu; Tor Ivar Simonsen; Gjermund Kittilsland; Birger Stark; Nils Hoivik; Vegar Dalsrud; Guttorm Salomonsen

doi:10.1149/1.3483495

Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometer Focal Plane Arrays

ECS Transactions ◽

10.1149/1.3483495 ◽

2019 ◽

Vol 33 (4) ◽

pp. 73-82 ◽

Cited By ~ 11

Author(s):

Adriana Lapadatu ◽

Tor Ivar Simonsen ◽

Gjermund Kittilsland ◽

Birger Stark ◽

Nils Hoivik ◽

...

Keyword(s):

Focal Plane ◽

Focal Plane Arrays ◽

Wafer Level

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Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

Infrared Physics & Technology ◽

10.1016/j.infrared.2013.05.006 ◽

2013 ◽

Vol 60 ◽

pp. 251-259 ◽

Cited By ~ 10

Author(s):

Fredrik Forsberg ◽

Niclas Roxhed ◽

Andreas C. Fischer ◽

Björn Samel ◽

Per Ericsson ◽

...

Keyword(s):

Focal Plane ◽

Large Scale ◽

Vacuum Packaging ◽

Focal Plane Arrays ◽

Heterogeneous Integration ◽

Wafer Level

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Preparation of packaging cap with binary glass microlenses for wafer level packaging of Focal Plane Arrays (FPAs)

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging ◽

10.1109/icept.2010.5582653 ◽

2010 ◽

Cited By ~ 1

Author(s):

Chao Xu ◽

Jintang Shang ◽

Di Zhang ◽

Boyin Chen ◽

Junwen Liu

Keyword(s):

Focal Plane ◽

Focal Plane Arrays ◽

Wafer Level ◽

Wafer Level Packaging ◽

Binary Glass

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Enabling more capability within smaller pixels: advanced wafer-level process technologies for integration of focal plane arrays with readout electronics

10.1117/12.2054106 ◽

2014 ◽

Cited By ~ 1

Author(s):

Dorota S. Temple ◽

Erik P. Vick ◽

Matthew R. Lueck ◽

Dean Malta ◽

Mark R. Skokan ◽

...

Keyword(s):

Focal Plane ◽

Focal Plane Arrays ◽

Wafer Level ◽

Readout Electronics ◽

Level Process

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Three-Dimensional Integration Technology for Advanced Focal Planes

MRS Proceedings ◽

10.1557/proc-1112-e01-02 ◽

2008 ◽

Vol 1112 ◽

Cited By ~ 2

Author(s):

Craig Lewis Keast ◽

Brian Aull ◽

James Burns ◽

Chenson Chen ◽

Jeff Knecht ◽

...

Keyword(s):

Focal Plane ◽

Three Dimensional ◽

Focal Plane Arrays ◽

Silicon On Insulator ◽

Wafer Level ◽

Integration Technology ◽

Electrical Interconnection ◽

Circuit Integration ◽

Micrometer Scale ◽

Soi Technology

AbstractWe have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

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