Postannealing Process for Low Temperature Processed Sol–Gel Zinc Tin Oxide Thin Film Transistors

2010 ◽  
Vol 13 (10) ◽  
pp. H357 ◽  
Author(s):  
Seok-Jun Seo ◽  
Young Hwan Hwang ◽  
Byeong-Soo Bae
2013 ◽  
Vol 62 (8) ◽  
pp. 1176-1182 ◽  
Author(s):  
Jong Hoon Lee ◽  
Chang Hoi Kim ◽  
Hong Seung Kim ◽  
Jae Hoon Park ◽  
Jin Hwa Ryu ◽  
...  

2011 ◽  
Vol 99 (15) ◽  
pp. 152102 ◽  
Author(s):  
Seok-Jun Seo ◽  
Jun Hyuck Jeon ◽  
Young Hwan Hwang ◽  
Byeong-Soo Bae

2012 ◽  
Vol 2 (1) ◽  
pp. 17-22 ◽  
Author(s):  
Jun-Hyuck Jeon ◽  
Young Hwan Hwang ◽  
JungHo Jin ◽  
Byeong-Soo Bae

Abstract


2010 ◽  
Vol 1247 ◽  
Author(s):  
Chen-Guan Lee ◽  
Soumya Dutta ◽  
Ananth Dodabalapur

AbstractWe demonstrate high performance zinc-tin oxide (ZTO) thin-film transistors (TFTs) with low operation voltage, small channel length and low parasitic capacitance. Both the zinc tin oxide and the high-k dielectric, ZrO2, were solution processed by sol-gel methods. A self-aligned process was employed to minimize the parasitic capacitance. The transistors with a channel length of 8 μm operate at 5 V and have a saturation mobility of 2.5 cm2/V·s and an on/off ratio of 5.9×106. Gate-induced surface relief has been found to have strong effect on the performance of the active layer.


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