Electrodeposition and Characterization of Eutectic Sn–Ag Alloy as Solder Bumps for Flip-Chip Interconnection

2009 ◽  
Vol 156 (10) ◽  
pp. D424 ◽  
Author(s):  
Yi Qin ◽  
G. D. Wilcox ◽  
Changqing Liu
Keyword(s):  
Flip Chip ◽  
Solder Bumps

Characterization of Epoxy-Functionalized Silsesquioxanes as Potential Underfill Encapsulants

1998 ◽  
Vol 519 ◽  
Author(s):  
E. K. Lin ◽  
C. R. Snyder ◽  
F. I. Mopsik ◽  
W. E. Wallace ◽  
W. L. Wu ◽  
...  
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Silica Particles ◽  
Critical Parameters ◽  
Organic Hybrid ◽  
Solder Bumps ◽  
The Difference ◽  
Electronics Packages

AbstractIn electronics packaging, underfill encapsulants are needed to improve package reliability in flip-chip devices. The underfill generally consists of an epoxy resin highly filled with silica particles and is designed to reduce the stress arising from the difference in the thermal expansion between the solder bumps and the substrate. Currently, concerns about the flow of the silica particles and surface phenomena are arising as electronics packages reduce in size. Newly developed epoxy-functionalized octameric silsesquioxanes provide an intriguing alternative to current formulations. These single-phase inorganic/organic hybrid materials may have properties similar to filled materials without the complications from the rheology of filled materials. The physical properties of the functionalized silsesquioxanes are measured with respect to the critical parameters for underfill materials. Measurements of properties such as the coefficient of thermal expansion and density are performed to evaluate the suitability of these materials as potential underfill encapsulants.

Thermal conduction analysis and characterization of solder bumps in flip chip package

2012 ◽  
Vol 36 ◽  
pp. 181-187 ◽  
Author(s):  
Xiangning Lu ◽  
Tielin Shi ◽  
Qi Xia ◽  
Guanglan Liao
Keyword(s):  
Thermal Conduction ◽  
Flip Chip ◽  
Solder Bumps

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Emerging Techniques for the Characterization of Nano-Mechanical Properties of Integrated Circuit Components

2008 ◽  
Author(s):  
Nicholas Randall ◽  
Rahul Premachandran Nair
Keyword(s):  
Mechanical Properties ◽  
Quality Control ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Manufacturing Process ◽  
Solder Bumps ◽  
Initial Work ◽  
Circuit Components ◽  
Materials Used

Abstract With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

scholarly journals Demonstration of fine pitch FCOB (Flip Chip on Board) assembly based on solder bumps at Fermilab

2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  
Flip Chip ◽  
Fine Pitch ◽  
Solder Bumps

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

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