Design of High-k Interfacial Layer Formation by Cycle-by-Cycle Deposition and Annealing Method

2019 ◽  
Vol 19 (2) ◽  
pp. 129-143 ◽  
Author(s):  
Arito Ogawa ◽  
Kunihiko Iwamoto ◽  
Hiroyuki Ota ◽  
Masashi Takahashi ◽  
Akito Hirano ◽  
...  
Keyword(s):  
Interfacial Layer ◽  
Layer Formation ◽  
High K ◽  
Annealing Method

High quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack

2020 ◽  
Vol 223 ◽  
pp. 111219 ◽  
Author(s):  
S. Siddiqui ◽  
R. Galatage ◽  
W. Zhao ◽  
G. Raja Muthinti ◽  
J. Fronheiser ◽  
...  
Keyword(s):  
Interfacial Layer ◽  
Layer Formation ◽  
Metal Gate ◽  
Gate Stack ◽  
High Quality ◽  
High K

Application of ultraviolet radiation to minimize interfacial layer formation during the growth of alternate high-k gate dielectrics on Si

2001 ◽  
Vol 666 ◽  
Author(s):  
V. Craciun ◽  
N. D. Bassim ◽  
J. M. Howard ◽  
J. Spear ◽  
S. Bates ◽  
...  
Keyword(s):  
Uv Radiation ◽  
Oxygen Pressure ◽  
Interfacial Layer ◽  
Silicon Oxide ◽  
Gate Dielectrics ◽  
Laser Deposition ◽  
Layer Formation ◽  
Si Substrates ◽  
Barium Strontium ◽  
High K

ABSTRACTYttrium oxide and barium strontium titanate (BST) thin films were grown directly on Si substrates by the pulsed laser deposition (PLD) technique. Because the optimum oxygen pressure during PLD process is of the order of 10 mTorr, some of the oxygen atoms are trapped inside the grown films and contribute to the growth of a silicon oxide interfacial layer. The use of an UV source during the growth resulted in the reduction of the optimum oxygen pressure and, as a consequence, the amount of trapped oxygen and thickness of the interfacial layer. In addition to that, UV radiation influenced the film morphologies and electrical properties. A further reduction of the interfacial layer was obtained on substrates that were exposed prior to deposition to NH3 for short periods of time under UV radiation.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Effect of inner oxygen on the interfacial layer formation for HfO2 gate dielectric

2007 ◽  
Vol 42 (17) ◽  
pp. 7343-7347 ◽  
Author(s):  
Ran Jiang ◽  
E. Q. Xie ◽  
Z. F. Wang
Keyword(s):  
Interfacial Layer ◽  
Gate Dielectric ◽  
Layer Formation

Counter Dipole Layer Formation in Multilayer High-$k$ Gate Stacks

2012 ◽  
Vol 51 ◽  
pp. 081303 ◽  
Author(s):  
Shinya Hibino ◽  
Tomonori Nishimura ◽  
Kosuke Nagashio ◽  
Koji Kita ◽  
Akira Toriumi
Keyword(s):  
Layer Formation ◽  
Gate Stacks ◽  
Dipole Layer ◽  
High K

Improved electrical characteristics of high-k gated MOSFETs with post-growth treatment on interfacial layer

2015 ◽  
Vol 138 ◽  
pp. 81-85 ◽  
Author(s):  
Dun-Bao Ruan ◽  
Kuei-Shu Chang-Liao ◽  
Chen-Chien Li ◽  
Chun-Chang Lu ◽  
Yu-Liang Liao ◽  
...  
Keyword(s):  
Interfacial Layer ◽  
Electrical Characteristics ◽  
High K
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