Analysis of Intrinsic and Parasitic Gate Delay of InGaAs HEMTs

2019 ◽  
Vol 16 (7) ◽  
pp. 65-72 ◽  
Author(s):  
Tetsuya Suemitsu
Keyword(s):  
Gate Delay

Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts

2021 ◽  
Author(s):  
Sujay Pandey ◽  
Zhiwei Liao ◽  
Shreyas Nandi ◽  
Suriyaprakash Natarajan ◽  
Arani Sinha ◽  
...  
Keyword(s):  
Gate Delay

SiGe HBT technology with fT/fmax of 300GHz/500GHz and 2.0 ps CML gate delay

2010 ◽  
Author(s):  
B. Heinemann ◽  
R. Barth ◽  
D. Bolze ◽  
J. Drews ◽  
G. G. Fischer ◽  
...  
Keyword(s):  
Gate Delay ◽  
Sige Hbt

An ECL 5000-gate gate array with 190-ps gate delay

1986 ◽  
Vol 21 (2) ◽  
pp. 234-239 ◽  
Author(s):  
M. Tatsuki ◽  
S. Kato ◽  
M. Okabe ◽  
H. Yakushiji ◽  
Y. Kuramitsu
Keyword(s):  
Gate Delay ◽  
Gate Array

SILICON ON RAISED INSULATOR FIELD EFFECT DIODE (SORI-FED) FOR ALLEVIATING SCALING PROBLEM IN FED

2014 ◽  
Vol 28 (05) ◽  
pp. 1450038 ◽  
Author(s):  
MAHDI VADIZADEH ◽  
MORTEZA FATHIPOUR ◽  
GHAFAR DARVISH
Keyword(s):  
Delay Time ◽  
Field Effect ◽  
Channel Length ◽  
Gate Delay ◽  
Electrical Characteristics ◽  
Band To Band Tunneling ◽  
Main Components ◽  
Channel Lengths ◽  
Length Scaling ◽  
The Impact

One of the main shortcomings in a field effect diode (FED) is its scaling. Use of an oxide layer in the channel is proposed to enhance the control of the gate on the channel carriers. This is the so-called silicon on raised insulator FED (SORI-FFD) structure. The Shockley–Read–Hall (SRH) mechanism is one of the main components of leakage current in FED devices. The potential induced by the gates in the OFF-state of a SORI-FFD, is larger than that induced by the gates of a regular FED. This reduces, SRH recombination rate. Hence, OFF-state characteristics of the SORI-FED device improves. We evaluate the impact of band-to-band tunneling (BTBT) on the electrical characteristics of Modified FED (M-FED).We show that for channel lengths of 35 nm and lower this device does not turn off. While, the proposed structure makes device channel length scaling possible down to 15 nm. We will also compare electrical characteristics of SORI-FED and M-FED using three metrics: gate delay time versus channel length, gate delay time versus I ON /I OFF ratio and energy-delay product versus channel length. Benchmarking results show the proposed FED structure provides improvement in I ON /I OFF ratio and holds promise for future logic transistor applications.

scholarly journals Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials

VLSI Design ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-7 ◽  
Author(s):  
Yin Li ◽  
Yu Zhang ◽  
Xiaoli Guo
Keyword(s):  
Time Delay ◽  
Special Class ◽  
Time Complexity ◽  
Space Complexity ◽  
Polynomial Basis ◽  
Gate Delay ◽  
Complexity Bound ◽  
Parallel Multiplier ◽  
Highly Efficient ◽  
First Time

Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, xm+xm/3+1. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about 2/3 circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept

2017 ◽  
Author(s):  
Assia El-Hadbi ◽  
Abdelkarim Cherkaoui ◽  
Oussama Elissati ◽  
Jean Simatic ◽  
Laurent Fesquet
Keyword(s):  
Gate Delay ◽  
Proof Of Concept

Statistical Gate-Delay Modeling with Copulas

2020 ◽  
Vol 15 (3) ◽  
pp. 1-10
Author(s):  
Walter Schneider
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Process Variations ◽  
Deep Submicron ◽  
Experimental Results ◽  
Gate Delay ◽  
Integrated Circuit Design ◽  
Circuit Performance ◽  
Delay Models ◽  
Innovative Concept

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

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