Improving Threshold Voltage and Device Performance of Gate-First HfSiON/Metal Gate n-MOSFETs by an ALD La[sub 2]O[sub 3] Capping Layer

2008 ◽  
Vol 155 (6) ◽  
pp. H373 ◽  
Author(s):  
Satoshi Kamiyama ◽  
Etsuo Kurosawa ◽  
Yasuo Nara
Keyword(s):  
Threshold Voltage ◽  
Device Performance ◽  
Metal Gate ◽  
Capping Layer

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

2021 ◽  
Author(s):  
Amit Kumar ◽  
Anil Kumar Rajput ◽  
Manisha Pattanaik ◽  
Pankaj Srivast
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Analytical Modelling ◽  
Device Performance ◽  
Oxide Material ◽  
Metal Gate ◽  
Drain Region ◽  
Dual Metal ◽  
Nitride Oxide ◽  
Potential Threshold

Abstract In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.

Effect of Gate Metal Work-function on Junctionless (JL) Nanowire GAA MOSFET Performance

2021 ◽  
Author(s):  
Manoj Angara ◽  
Biswajit Jena ◽  
S. Rooban
Keyword(s):  
Work Function ◽  
Threshold Voltage ◽  
Drain Current ◽  
Potential Profile ◽  
Device Performance ◽  
Metal Gate ◽  
Metal Work Function ◽  
Current Threshold ◽  
Source Voltage ◽  
Metal Work

Abstract Metal gate technology is one of the promising methods used to increase the drain current by increasing the electrostatic controllability. Different metals have different work-function that controls the device performance very closely as gate to source voltage is the basic inputs for these. In this paper the dependency of gate metal work-function on device performance (both for nMOS and pMOS) is extensively investigated. The gate metal work-function value is taken as 4.2eV to 5.1eV with one increment to see the change in potential profile. With this condition, the IOn current, IOff current, threshold voltage, transconductance also calculated for these structures. A decrease value in drain current (1e-6 to 1e-7 A) is observed for both the cases with increase in work-function of gate metal. However, the Off current is getting better (1e-7 to 1e-18 A) while moving towards higher metal work-function values. As a result of which the IOn/IOff ratio increases which leads to higher device performances.

Hydrogen Concentration Analysis in Pecvd and Rtcvd Silicon Nitride Thin Films and It's Impact on Device Performance

2001 ◽  
Vol 664 ◽  
Author(s):  
C. Y. Wang ◽  
E. H. Lim ◽  
H. Liu ◽  
J. L. Sudijono ◽  
T. C. Ang ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Threshold Voltage ◽  
Vapor Deposition ◽  
Gas Flow ◽  
Chemical Vapor ◽  
Gate Oxide ◽  
Nitride Film ◽  
Device Performance ◽  
Gas Flow Ratio ◽  
The Impact

ABSTRACTIn this paper the impact of the ESL (Etch Stop layer) nitride on the device performance especially the threshold voltage (Vt) has been studied. From SIMS analysis, it is found that different nitride gives different H concentration, [H] in the Gate oxide area, the higher [H] in the nitride film, the higher H in the Gate Oxide area and the lower the threshold voltage. It is also found that using TiSi instead of CoSi can help to stop the H from diffusing into Gate Oxide/channel area, resulting in a smaller threshold voltage drift for the device employed TiSi. Study to control the [H] in the nitride film is also carried out. In this paper, RBS, HFS and FTIR are used to analyze the composition changes of the SiN films prepared using Plasma enhanced Chemical Vapor deposition (PECVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) with different process parameters. Gas flow ratio, RF power and temperature are found to be the key factors that affect the composition and the H concentration in the film. It is found that the nearer the SiN composition to stoichiometric Si3N4, the lower the [H] in SiN film because there is no excess silicon or nitrogen to be bonded with H. However the lowest [H] in the SiN film is limited by temperature. The higher the process temperature the lower the [H] can be obtained in the SiN film and the nearer the composition to stoichiometric Si3N4.

Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

2013 ◽  
Vol 103 (20) ◽  
pp. 203501 ◽  
Author(s):  
Uio-Pu Chiou ◽  
Jia-Min Shieh ◽  
Chih-Chao Yang ◽  
Wen-Hsien Huang ◽  
Yo-Tsung Kao ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Metal Gate ◽  
Si Thin Film ◽  
Nanocrystalline Si

Impact of interface trap charges on Junctionless double and triple metal gate High-k Gate All Around Nanowire FET based Alzheimer Biosensor

2021 ◽  
Author(s):  
Rishu Chaujar ◽  
Mekonnen Getnet Yirak
Keyword(s):  
Threshold Voltage ◽  
Positive Impact ◽  
Drain Current ◽  
Interface Trap ◽  
Metal Gate ◽  
High K ◽  
Current Threshold ◽  
Subthreshold Voltage ◽  
Output Characteristics ◽  
The Impact

Abstract In this work, junctionless double and triple metal gate high-k gate all around nanowire field-effect transistor-based APTES biosensor has been developed to study the impact of ITCs on device sensitivity. The analytical results were authenticated using ‘‘ATLAS-3D’’ device simulation tool. Effect of different interface trap charge on the output characteristics of double and triple metal gate high-k gate all around junctionless NWFET biosensor was studied. Output characteristics, like transconductance, output conductance,drain current, threshold voltage, subthreshold voltage and switching ratio, including APTES biomolecule, have been studied in both devices. 184% improvement has been investigated in shifting threshold voltage in a triple metal gate compared to a double metal gate when APTES biomolecule immobilizes on the nanogap cavity region under negative ITCs. Based on this finding, drain off-current ratio and shifting threshold voltage were considered as sensing metrics when APTES biomolecule immobilizes in the nanogap cavity under negative ITCs which is significant for Alzheimer's disease detection. We signifies a negative ITC has a positive impact on our proposed biosensor device compared to positive and neutral ITCs.

Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling

2021 ◽  
Vol 314 ◽  
pp. 119-126
Author(s):  
Yusuke Oniki ◽  
Lars Åke Ragnarsson ◽  
Hideaki Iino ◽  
Daire Cott ◽  
Boon Teik Chan ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Metal Gate ◽  
Unit Process ◽  
Device Scaling ◽  
Interface Dipole ◽  
Device Integration ◽  
Multiple Threshold ◽  
Long Channel

This paper addresses challenges and solutions of replacement metal gate of gate-all-around nanosheet devices. The unit process and integration solutions for the metal gate patterning as well as interface dipole patterning to offer multiple threshold voltage have been developed. The challenges of long channel device integration are also discussed.

On the positive channel threshold voltage of metal gate electrodes on high-permittivity gate dielectrics

2007 ◽  
Vol 102 (7) ◽  
pp. 074511 ◽  
Author(s):  
J. K. Schaeffer ◽  
D. C. Gilmer ◽  
S. Samavedam ◽  
M. Raymond ◽  
A. Haggag ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Dielectrics ◽  
Metal Gate Electrodes ◽  
Metal Gate ◽  
High Permittivity ◽  
Gate Electrodes
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