Post Cu-CMP Engineering Challenges for the 65 nm Technology Nodes and Beyond

2019 ◽  
Vol 11 (2) ◽  
pp. 431-440 ◽  
Author(s):  
Sebastien Petitdidier ◽  
Maxime Mellier ◽  
Denis Guiheux ◽  
Marc Juhel
Keyword(s):  
Technology Nodes ◽  
Cu Cmp

BEOL Cu CMP Process Evaluation for Advanced Technology Nodes

2013 ◽  
Vol 160 (12) ◽  
pp. D3247-D3254 ◽  
Author(s):  
Kunaljeet Tanwar ◽  
Donald Canaperi ◽  
Michael Lofaro ◽  
Wei-tsu Tseng ◽  
Raghuveer Patlolla ◽  
...  
Keyword(s):  
Process Evaluation ◽  
Advanced Technology ◽  
Technology Nodes ◽  
Cu Cmp

Post Cu CMP cleaning process evaluation for 32nm and 22nm technology nodes

2012 ◽  
Author(s):  
Wei-Tsu Tseng ◽  
D. Canaperi ◽  
A. Ticknor ◽  
V. Devarapalli ◽  
L. Tai ◽  
...  
Keyword(s):  
Process Evaluation ◽  
Cleaning Process ◽  
Technology Nodes ◽  
Cu Cmp

Reducing density-induced CMP non-uniformity for advanced semiconductor technology nodes

2013 ◽  
Vol 1560 ◽  
Author(s):  
John H Zhang ◽  
Wei-Tsu Tseng ◽  
Tien Chen ◽  
Ben Kim ◽  
Philip Flaitz ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
The Difference ◽  
Technology Nodes ◽  
Cu Cmp ◽  
Space Width ◽  
Line Space ◽  
Selection Of

ABSTRACTIn this paper, a novel set of macros with line/space width from 128nm/128nm, 64nm/64nm to 32nm/32nm was designed and installed on 20nm technology-node hardware. The pitch-dependent pad erosion post Cu CMP was studied by atomic-force microscopy (AFM), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) quantitatively on these macros. Two methods were investigated to reduce the difference between pitch- and density-induced CMP non-uniformity. The first is using new scheme of partial Cu plating process followed by SiCNH insulator deposition and then CMP. The second is through the selection of slurries and pads. Both results are discussed in this paper.

Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

2009 ◽  
Author(s):  
E. Hendarto ◽  
S.L. Toh ◽  
J. Sudijono ◽  
P.K. Tan ◽  
H. Tan ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Focused Ion Beam ◽  
Failure Modes ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Nickel Silicide ◽  
Fault Isolation ◽  
Technology Nodes ◽  
Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Dynamic Photon Emission on FinFET Devices Through Novel Scan Test Approaches

2019 ◽  
Author(s):  
Ranganathan Gopinath ◽  
Ravikumar Venkat Krishnan ◽  
Lua Winson ◽  
Phoa Angeline ◽  
Jin Jie
Keyword(s):  
Test Pattern ◽  
Photon Emission ◽  
Pattern Generator ◽  
Lower Probability ◽  
Automated Test Equipment ◽  
Use Patterns ◽  
Infra Red ◽  
Automatic Test Pattern Generator ◽  
Technology Nodes ◽  
Established Technique

Abstract Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

SEM-Based Nanoprobing on 40, 32 and 28 nm CMOS Devices Challenges for Semiconductor Failure Analysis

2013 ◽  
Author(s):  
Erik Paul ◽  
Holger Herzog ◽  
Sören Jansen ◽  
Christian Hobert ◽  
Eckhard Langer
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
Case Studies ◽  
State Of The Art ◽  
Root Cause ◽  
Highly Efficient ◽  
Technology Nodes ◽  
Scanning Electron

Abstract This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation

2016 ◽  
Author(s):  
Ramya Yeluri ◽  
Ravishankar Thirugnanasambandam ◽  
Cameron Wagner ◽  
Jonathan Urtecho ◽  
Jan M. Neirynck
Keyword(s):  
Duty Cycle ◽  
Thermal Effects ◽  
Second Harmonic ◽  
Fault Isolation ◽  
Advanced Technology ◽  
Temperature Dependent ◽  
First Case ◽  
Improve Accuracy ◽  
Degradation Monitoring ◽  
Technology Nodes

Abstract Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing

2012 ◽  
Author(s):  
P. Larré ◽  
H. Tupin ◽  
C. Charles ◽  
R.H. Newton ◽  
A. Reverdy
Keyword(s):  
Electron Beam ◽  
Failure Analysis ◽  
Test Structure ◽  
Precise Localization ◽  
Isolation Method ◽  
Accurate Detection ◽  
Conventional Methods ◽  
Technology Nodes ◽  
Tem Lamella

Abstract As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.

Sign in / Sign up

Export Citation Format

Share Document