Impact of Metal Silicide Layout Covering Source/Drain Diffusions on Parasitic Resistance of Triple-Gate SOI MOSFET

2019 ◽  
Vol 6 (4) ◽  
pp. 27-32 ◽  
Author(s):  
Kazuhisa Yoshimoto ◽  
Y. Omura ◽  
Hitoshi Wakabayashi
Keyword(s):  
Metal Silicide ◽  
Soi Mosfet ◽  
Parasitic Resistance

Digital image processing methods applied to the study of annealing time on semiconductor-metal eutectic composites

1988 ◽  
Vol 46 ◽  
pp. 848-849
Author(s):  
J. Hefter
Keyword(s):  
Image Processing ◽  
Digital Image Processing ◽  
Digital Image ◽  
Electronic Device ◽  
Processing System ◽  
Average Diameter ◽  
Eutectic Solidification ◽  
Metal Silicide ◽  
The Matrix ◽  
Microscopic Studies

Semiconductor-metal composites, formed by the eutectic solidification of silicon and a metal silicide have been under investigation for some time for a number of electronic device applications. This composite system is comprised of a silicon matrix containing extended metal-silicide rod-shaped structures aligned in parallel throughout the material. The average diameter of such a rod in a typical system is about 1 μm. Thus, characterization of the rod morphology by electron microscope methods is necessitated.The types of morphometric information that may be obtained from such microscopic studies coupled with image processing are (i) the area fraction of rods in the matrix, (ii) the average rod diameter, (iii) an average circularity (roundness), and (iv) the number density (Nd;rods/cm2). To acquire electron images of these materials, a digital image processing system (Tracor Northern 5500/5600) attached to a JEOL JXA-840 analytical SEM has been used.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

Controlling of Floating-Body and Thermal Conductivity in Short Channel SOI MOSFET at 30 nm Channel Node

Silicon ◽  
2021 ◽  
Author(s):  
Pradipta Dutta ◽  
SubhashreeSoubhagyamayee Behera ◽  
Soumendra Prasad Rout
Keyword(s):  
Thermal Conductivity ◽  
Floating Body ◽  
Short Channel ◽  
Soi Mosfet

Interface effects in the formation of silicon oxide on metal silicide layers over silicon substrates

1983 ◽  
Vol 54 (4) ◽  
pp. 1849-1854 ◽  
Author(s):  
J. E. E. Baglin ◽  
F. M. d’Heurle ◽  
C. S. Petersson
Keyword(s):  
Silicon Oxide ◽  
Silicon Substrates ◽  
Metal Silicide ◽  
Interface Effects

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

2008 ◽  
Vol 55 (3) ◽  
pp. 789-795 ◽  
Author(s):  
Pradeep Agarwal ◽  
Govind Saraswat ◽  
M. Jagadesh Kumar
Keyword(s):  
Surface Potential ◽  
Potential Model ◽  
Depletion Region ◽  
Compact Surface ◽  
Soi Mosfet
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