Impact of Al, Ni, and TiN Metal Gates On ZrO2-MOS Capacitors

2019 ◽  
Vol 1 (5) ◽  
pp. 507-515 ◽  
Author(s):  
Stephan M. Abermann ◽  
Joseph Efavi ◽  
Alois Lugstein ◽  
Erwin Auer ◽  
Heiner Gottlob ◽  
...  
Keyword(s):  
2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.


1999 ◽  
Vol 567 ◽  
Author(s):  
B. Claflin ◽  
K. Flock ◽  
G. Lucovsky

ABSTRACTSeveral metal and conducting metal nitride candidates were investigated for alternative gate electrode applications in future complimentary metal-oxide-semiconductor (CMOS) devices. High frequency capacitance-voltage (CV) measurements were performed on n-MOS and p-MOS capacitors with Al, Ta, TaN, TIN, or W2N gates and ultra-thin SiO2/Si3N4 dielectric stacks. The work functions of Al and Ta were close to the conduction band of Si as expected while all the metal nitrides had work functions slightly above mid-gap. The thermal stability of the metal nitrides and the metal/dielectric interfaces was studied by Auger electron spectroscopy (AES) following rapid thermal annealing (RTA). Integration requirements for dual metal gate electrodes in future CMOS devices are discussed.


Author(s):  
Kosuke Tatsumura ◽  
Masakazu Goto ◽  
Shigeru Kawanaka ◽  
Kazuaki Nakajima ◽  
Tatsuo Schimizu ◽  
...  
Keyword(s):  

1998 ◽  
Vol 532 ◽  
Author(s):  
B. Claflin ◽  
M. Binger ◽  
G. Lucovsky ◽  
H.-Y. Yang

ABSTRACTThe growth of reactively sputtered TiNx and WNx compound metal films on ultra-thin, remote plasma enhanced chemical vapor deposited SiO2 and SiO2/Si3N4 (ON) stack dielectrics is investigated from initial interface formation to bulk film by interrupted growth and on-line Auger electron spectroscopy (AES). Growth of both metals occurs uniformly without a seed layer on both dielectrics. The chemical stability of these metal/dielectric interfaces is studied by sequential on-line rapid thermal annealing treatments up to 850 °C and AES. TiNx reacts with SiO2 above 850 °C but the addition of a Si3N4 dielectric top-layer makes the TiNx/ON interface chemically stable at 850 °C. WNx/SiO2 and WNx/Si3N4 interfaces are both stable below 650 °C. MOS capacitors using TiNx or WNx metal gates and thermal SiO2 gate dielectrics exhibit excellent capacitance-voltage characteristics. The work function for TiNx lies near midgap in Si while for WNx it lies closer to the valence band.


2002 ◽  
Vol 716 ◽  
Author(s):  
S.B. Samavedam ◽  
J.K. Schaeffer ◽  
D.C. Gilmer ◽  
V. Dhandapani ◽  
P.J. Tobin ◽  
...  

AbstractAs the MOSFET gate lengths are scaled down to 50 nm or below, the expected increase in gate leakage will be countered by the use of a high dielectric constant (high K) material. The series capacitance from polysilicon gate electrode depletion significantly reduces the gate capacitance as the dielectric thickness is scaled down to 10 Å equivalent oxide thickness (EOT) or below. Metal gates promise to solve this problem and address other problems like boron penetration and enhanced gate resistance that will have increased focus as the polysilicon gate thickness is reduced. Extensive simulations have shown that the optimal gate work-functions for the sub-50 nm channel lengths should be 0.2 eV below (above) the conduction (valence) band edge of silicon for n-MOSFETs (p-MOSFETs). This study summarizes the evaluations of TiN, TaSiN, WN, TaN, TaSi, Ir and IrO2 as candidate metals for dual-metal gate CMOS using HfO2 as the gate dielectric. The gate work-function was determined by fabricating MOS capacitors with varying dielectric thicknesses and different post-gate anneals. The metal-dielectric compatibility and thermal stability was studied by annealing the stacks at different temperatures. The gate stacks were characterized using TEM, SIMS and X-ray diffraction. Based on workfunctions and thermal stability, TaSiN and TaN show most promise as metal electrodes for HfO2 n-MOSFETs.


2014 ◽  
Vol 35 (8) ◽  
pp. 811-813 ◽  
Author(s):  
Lichuan Zhao ◽  
Zhaoyun Tang ◽  
Bo Tang ◽  
Xueli Ma ◽  
Jinbiao Liu ◽  
...  

2015 ◽  
Vol 118 (4) ◽  
pp. 045307 ◽  
Author(s):  
Christopher J. Brennan ◽  
Christopher M. Neumann ◽  
Steven A. Vitale

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