Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

2015 ◽  
Vol 118 (4) ◽  
pp. 045307 ◽  
Author(s):  
Christopher J. Brennan ◽  
Christopher M. Neumann ◽  
Steven A. Vitale
Keyword(s):  
Gate Dielectric ◽  
Atomic Layer ◽  
Plasma Damage ◽  
Metal Gates ◽  
Tin Metal

Correlation of Phase Segregation and Electrical Properties of Low-Power MOSFETs with Hf-based Silicate Gate Dielectric Layers and TaN Metal Gates

2006 ◽  
Vol 917 ◽  
Author(s):  
Jasmine Petry ◽  
Chris Rittersma ◽  
Georgios Vellianitis ◽  
Vincent Cosnier ◽  
Thierry Conard ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Gate Dielectric ◽  
Phase Segregation ◽  
Atomic Layer ◽  
Gate Leakage ◽  
Electrical Measurements ◽  
Metal Gates ◽  
Fourier Transformed Infrared Spectroscopy ◽  
Transmission Electron ◽  
Layer Deposition

AbstractThe need for nitridation of Hf silicate is controversial. On one hand, it has not been proven that the nitridation is mandatory to have working devices and on the other hand, it is known to increase the charge density. In this paper, we present a detailed comprehensive study of the role and the need for nitridation of Hf-based silicates deposited by Atomic Layer Deposition (ALD). The results are based on a correlation of Fourier-Transformed Infrared Spectroscopy (FT-IR), X-ray Photoelectron Spectroscopy (XPS), High-resolution Transmission Electron Microscopy (HR-TEM) and electrical measurements (gate leakage and mobility).It was observed that the phase segregation in gate dielectrics is not detrimental for the gate leakage density at room temperature. However, the leakage current is significantly increased at higher temperature. The incorporation of nitrogen was either done by NH3 anneal (at 800C) or by Decoupled Plasma Nitridation (DPN – 25.9kJ). While the DPN or NH3 anneal prevent phase segregation for 50% Hf silicate, only the NH3 anneal helps prevent the phase segregation of Hf-rich silicate. Furthermore, the NH3 anneal increases the interfacial thickness, which produces a very low gate leakage with only 10% loss in mobility at high field. Interestingly, DPN followed by O2 anneal leads to an advantageous phase segregation of the Hf-rich silicate by transforming the silicate in a HfO2/SiO2-like stack.As a conclusion, not only the phase segregation of the silicate does not always lead to shorted devices, but it can be beneficial in terms of mobility. However, the phase segregation seems to be responsible for an enlarged trap-assisted conduction mechanism at high temperature. But even if the 50% Hf silicates non-nitrided leads to working devices, the incorporation of nitrogen in the stack improves the Jg/CET trends and is therefore beneficial.

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Composition Quantification of Microelectronics Multilayer Thin Films by EDX: Toward Small Scale Analysis

2009 ◽  
Vol 1184 ◽  
Author(s):  
Thierry Conard ◽  
Kai Arstila ◽  
Thomas Hantschel ◽  
Alexis Franquet ◽  
Wilfried Vandervorst ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Small Scale ◽  
Quantitative Composition ◽  
Composition Analysis ◽  
Multilayer Thin Films ◽  
Large Area ◽  
Fast Analysis ◽  
Metal Gates ◽  
High K ◽  
High K Materials

AbstractIn order to continuously improve the performances of microelectronics devices through scaling, SiO2 is being replaced by high-k materials as gate dielectric; metal gates are replacing poly-Si. This leads to increasingly more complex stacks. For future generations, the replacement of Si as a substrate by Ge and/or III/V material is also considered. This also increases the demand on the metrology tools as a thorough characterization, including composition and thickness is thus needed. Many different techniques exist for composition analysis. They usually require however large area for the analysis, complex instrumentation and can be time consuming. EDS (Energy Dispersive Spectroscopy) when coupled to Scanning Electron Microscopy (SEM) has the potential to allow fast analysis on small scale areas.In this work, we evaluate the possibilities of EDS for thin film analysis based on an intercomparison of composition analysis with different techniques. We show that using proper modeling, high quality quantitative composition and thickness of multilayers can be achieved.

scholarly journals Electrical Characterization of Postmetal Annealed Ultrathin TiN Gate Electrodes in Si MOS Capacitors

2016 ◽  
Vol 2016 ◽  
pp. 1-4 ◽  
Author(s):  
Z. N. Khan ◽  
S. Ahmed ◽  
M. Ali
Keyword(s):  
Electrical Characterization ◽  
Atomic Layer ◽  
Device Fabrication ◽  
Process Window ◽  
Gate Stacks ◽  
Mos Capacitors ◽  
Hafnium Silicate ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Tin Metal

Focusing on sub-10 nm Silicon CMOS device fabrication technology, we have incorporated ultrathin TiN metal gate electrode in Hafnium Silicate (HfSiO) based metal-oxide capacitors (MOSCAP) with carefully chosen Atomic Layer Deposition (ALD) process parameters. Gate element of the device has undergone a detailed postmetal annealed sequence ranging from 100°C to 1000°C. The applicability of ultrathin TiN on gate electrodes is established through current density versus voltage (J-V), resistance versus temperature (R-T), and permittivity versus temperature analysis. A higher process window starting from 600°C was intentionally chosen to understand the energy efficient behavior expected from ultrathin gate metallization and its unique physical state with shrinking thickness. The device characteristics in form of effective electronic mobility as a function of inverse charge density were also found better than those conventional gate stacks used for EOT scaling.

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

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