Evaluation of Evaporated Zn x Pb1 − x  S  as a Gate Insulator for HgCdTe Metal‐Insulator‐Semiconductor (MIS) Devices

1989 ◽  
Vol 136 (10) ◽  
pp. 3057-3060 ◽  
Author(s):  
Tom Orent
Keyword(s):  
Gate Insulator ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Mis Devices

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO2/SiN

2020 ◽  
Vol 20 (8) ◽  
pp. 4678-4683
Author(s):  
Jun Hyeok Jung ◽  
Min Su Cho ◽  
Won Douk Jang ◽  
Sang Ho Lee ◽  
Jaewon Jang ◽  
...  
Keyword(s):  
Electron Mobility ◽  
High Electron Mobility Transistor ◽  
Gate Insulator ◽  
High Electron ◽  
Insulator Layer ◽  
Metal Insulator ◽  
High Electron Mobility ◽  
Metal Insulator Semiconductor ◽  
Dual Gate ◽  
Recessed Gate

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm2, and a breakdown voltage of 631 V at an off-state current of 1 μA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

An Appropriate Diffusion Process Changes the Behaviour of a Planar-Nothing on Insulator Device

2020 ◽  
Vol 399 ◽  
pp. 115-122
Author(s):  
Cristian Ravariu ◽  
Elena Manea ◽  
Catalin Parvulescu
Keyword(s):  
Diffusion Process ◽  
Field Effect ◽  
Critical Issue ◽  
Gate Insulator ◽  
Related Structure ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Tunneling Currents

The paper investigates the tunneling currents through the gate terminals of the last MOSFET production and proposes a related structure, noted as p-NOI (planar-Nothing On Insulator) device. In fact, the p-NOI structure can arise as parasitic device in any MOSFET having a gate insulator sub-10nm thickness or can be separately produced to offer a tunneling device. The work principle of a p-NOI structure consists in the Fowler-Nordheim's tunneling of a thin insulator. Its architecture is derived from the Nothing On Insulator (NOI) device, using oxide instead vacuum. Essentially, the p-NOI current follows a metal-insulator-semiconductor trajectory. A critical issue is the field effect of a transistor that must be fulfilled by independent p-NOI device. In this purpose, a diffusion process seems to be the key. A planar p-NOI device with top three terminals is proposed. A diffusion process along to the Si-surface is a key technological step that offers distinct current traces.

Sign in / Sign up

Export Citation Format

Share Document