scholarly journals (Invited) White-Light-Induced Annihilation of Percolation Paths in SiO2 and High-k Dielectrics - Prospect for Gate Oxide Reliability Rejuvenation and Optical-Enabled Functions in CMOS Integrated Circuits

2015 ◽  
Vol 69 (5) ◽  
pp. 169-181 ◽  
Author(s):  
D. S. Ang ◽  
T. Kawashima ◽  
Y. Zhou ◽  
K. S. Yew ◽  
M. K. Bera ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
White Light ◽  
Gate Oxide ◽  
Cmos Integrated Circuits ◽  
Oxide Reliability ◽  
High K

Investigation of gate oxide breakdown in CMOS integrated circuits

1989 ◽  
Vol 20 (6) ◽  
pp. 19-26 ◽  
Author(s):  
B. Peŝić ◽  
S. Dimitrijev ◽  
N. Stojadinović
Keyword(s):  
Integrated Circuits ◽  
Gate Oxide ◽  
Cmos Integrated Circuits ◽  
Oxide Breakdown

Impact of Electrodes on Gate Oxide Reliability: Examples from Isolation and Gate-Stack Processing

1997 ◽  
Vol 473 ◽  
Author(s):  
D. L. Chapek ◽  
K. F. Schuegraf ◽  
R. P. S. Thakur
Keyword(s):  
Integrated Circuits ◽  
Bottom Electrode ◽  
Gate Oxide ◽  
Review Of Literature ◽  
Gate Stack ◽  
Oxide Reliability ◽  
Dielectric System ◽  
Thin Oxide ◽  
The Impact

ABSTRACTThis paper discusses the challenges involved in improving gate oxide reliability for advanced integrated circuits through review of literature and other relevant data. We believe that gate oxide reliability improvements can be engineered by paying special attention to the process conditioning of the top and bottom electrode components of the thin oxide dielectric system in advanced ULSI technologies. We present examples that demonstrate the impact of process and materials on the performance of thin oxide. The data encompasses the effects of substrate, isolation, and top electrodes on gate oxide quality using a variety of methodologies to assess reliability.

High-k gate stacks for planar, scaled CMOS integrated circuits

2003 ◽  
Vol 69 (2-4) ◽  
pp. 152-167 ◽  
Author(s):  
H.R. Huff ◽  
A. Hou ◽  
C. Lim ◽  
Y. Kim ◽  
J. Barnett ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Cmos Integrated Circuits ◽  
Gate Stacks ◽  
High K ◽  
Scaled Cmos

Exploration of heavy ion irradiation effects on gate oxide reliability in power MOSFETs

1995 ◽  
Vol 35 (3) ◽  
pp. 603-608 ◽  
Author(s):  
S.R. Anderson ◽  
R.D. Schrimpf ◽  
K.F. Galloway ◽  
J.L. Titus
Keyword(s):  
Ion Irradiation ◽  
Gate Oxide ◽  
Heavy Ion ◽  
Irradiation Effects ◽  
Power Mosfets ◽  
Heavy Ion Irradiation ◽  
Oxide Reliability

scholarly journals A Study on the Effect of the Structural Parameters and Internal Mechanism of a Bilateral Gate-Controlled S/D Symmetric and Interchangeable Bidirectional Tunnel Field Effect Transistor

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Structural Parameters ◽  
Cmos Integrated Circuits ◽  
Region Length ◽  
Internal Mechanism ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Switching Characteristics

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

The impact of F contamination induced by the process on the gate oxide reliability

1998 ◽  
Vol 38 (2) ◽  
pp. 255-258 ◽  
Author(s):  
G Ghidini ◽  
C Clementi ◽  
D Drera ◽  
F Maugain
Keyword(s):  
Gate Oxide ◽  
Oxide Reliability ◽  
The Impact
Sign in / Sign up

Export Citation Format

Share Document