Study of Total Quantum Efficiency of Lateral SOI PIN Photodiodes with Back-Gate Bias, Intrinsic Length and Temperature Variation

2015 ◽  
Vol 66 (5) ◽  
pp. 101-107 ◽  
Author(s):  
C. Novo ◽  
J. Baptista ◽  
M. Guazzeli da Silveira ◽  
R. Giacomini ◽  
A. Afzalian ◽  
...  
Keyword(s):  
Temperature Variation ◽  
Quantum Efficiency ◽  
Gate Bias ◽  
Back Gate ◽  
Intrinsic Length ◽  
Pin Photodiodes

Operation of Lateral SOI PIN Photodiodes with Back-Gate Bias and Intrinsic Length Variation

2013 ◽  
Vol 53 (5) ◽  
pp. 121-126 ◽  
Author(s):  
C. Novo ◽  
R. Giacomini ◽  
A. Afzalian ◽  
D. Flandre
Keyword(s):  
Length Variation ◽  
Gate Bias ◽  
Back Gate ◽  
Intrinsic Length ◽  
Pin Photodiodes

scholarly journals Simulação e caracterização elétrica de dispositivos fotossensores implementados em tecnologia SOI

2020 ◽  
Author(s):  
◽  
Edson José Rodrigues
Keyword(s):  
Film Thickness ◽  
Quantum Efficiency ◽  
Linear Trend ◽  
Silicon Film ◽  
Physical Models ◽  
Light Sources ◽  
Light Emitting ◽  
Intrinsic Length ◽  
Pin Photodiodes ◽  
The Relationship

This work presents an analysis of the main performance characteristics of lateral PIN photodiodes implemented in thin layer SOI technology, when illuminated by wavelengths, in the range between blue and ultraviolet (UV), and subjected to temperature variations. Twodimensional numerical simulations were performed to analyze characteristics such as photocurrent, absorption, quantum efficiency, and responsivity. In this analysis, the influence of the variation between 40 nm and 500 nm of the silicon film thickness (tSi) and the intrinsic length region (Li) between 5 and 30 ?m was considered to evaluate the performance of the photodiode at different wavelengths, in the range blue and ultraviolet (UV). Different sets of physical models were studied in the simulations, to reproduce trends reported in the literature. Through experimental measurements of the intensities of incident powers as a function of distance, light sources were characterized using light-emitting diodes at wavelengths, UV (390 nm), violet (410 nm), and Blue (460 nm), adapted for providing light energy in the photosensitive region of experimental photodiodes also characterized for temperatures between 100 K and 400 K. The simulations show that there is a dependency relationship between the silicon film thickness and the intrinsic length region (Li), that when evaluated and scaled simultaneously it is possible to optimize the quantum efficiency and responsivity of the PIN SOI photodiodes in the definition technology for specific wavelength applications. The results show that the quantum efficiency around 28 % and responsiveness around 85 mA / W for a given technology showed the same trend as the experimental results, taking into account the wavelength and temperature range. The results also show an almost linear trend in the relationship between silicon film thickness (tSi) and absorption (light penetration depth), so that, in thinner silicon film thickness, the device will be more selective for low wavelengths, that is, closer to UV

Suppression of Timing Variations due to Random Dopant Fluctuation by Back-Gate Bias in a Nanometer CMOS Inverter

2020 ◽  
Vol 13 ◽  
Author(s):  
Kai Zhang ◽  
Weifeng Lü ◽  
Peng Si ◽  
Zhifeng Zhao ◽  
Tianyu Yu
Keyword(s):  
Monte Carlo ◽  
Integrated Circuits ◽  
Metal Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Cmos Inverter ◽  
Back Gate ◽  
Random Dopant Fluctuation ◽  
Random Dopant

Background: In state-of-the-art nanometer metal-oxide-semiconductor-field-effect- transistors (MOSFETs), optimization of timing characteristic is one of the major concerns in the design of modern digital integrated circuits. Objective: This study proposes an effective back-gate-biasing technique to comprehensively investigate the timing and its variation due to random dopant fluctuation (RDF) employing Monte Carlo methodology. Methods: To analyze RDF-induced timing variation in a 22-nm complementary metal-oxide semiconductor (CMOS) inverter, an ensemble of 1000 different samples of channel-doping for negative metal-oxide semiconductor (NMOS) and positive metal-oxide semiconductor (PMOS) was reproduced and the input/output curves were measured. Since back-gate bias is technology dependent, we present in parallel results with and without VBG. Results: It is found that the suppression of RDF-induced timing variations can be achieved by appropriately adopting back-gate voltage (VBG) through measurements and detailed Monte Carlo simulations. Consequently, the timing parameters and their variations are reduced and, moreover, that they are also insensitive to channel doping with back-gate bias. Conclusion: Circuit designers can appropriately use back-gate bias to minimize timing variations and improve the performance of CMOS integrated circuits.

Improved solar-blind external quantum efficiency of back-illuminated AlxGa1−xN heterojunction pin photodiodes

2002 ◽  
Vol 38 (15) ◽  
pp. 824 ◽  
Author(s):  
C.J. Collins ◽  
U. Chowdhury ◽  
M.M. Wong ◽  
B. Yang ◽  
A.L. Beck ◽  
...  
Keyword(s):  
Quantum Efficiency ◽  
External Quantum Efficiency ◽  
Solar Blind ◽  
Pin Photodiodes ◽  
Back Illuminated
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