High-Temperature Reverse-Bias Stressing of Thin Gate Oxides in Power Transistors

2014 ◽  
Vol 64 (8) ◽  
pp. 45-52
Author(s):  
S. A. Suliman ◽  
O. O. Awadelkarim ◽  
J. Hao ◽  
M. Rioux
Keyword(s):  
High Temperature ◽  
Reverse Bias ◽  
Gate Oxides ◽  
Power Transistors

Degradation mechanism of D-mode GaN HEMT based on high temperature reverse bias stress

2021 ◽  
Author(s):  
Meng Lu ◽  
Yiqiang Chen ◽  
Min Liao ◽  
Chang Liu ◽  
Shuaizhi Zheng ◽  
...  
Keyword(s):  
High Temperature ◽  
Reverse Bias ◽  
Degradation Mechanism ◽  
Bias Stress ◽  
Gan Hemt

End of life and acceleration modelling for power diodes under high temperature reverse bias stress

2016 ◽  
Vol 64 ◽  
pp. 458-463 ◽  
Author(s):  
O. Schilling ◽  
K. Leitner ◽  
K.-D. Schulze ◽  
F. Umbach
Keyword(s):  
High Temperature ◽  
End Of Life ◽  
Reverse Bias ◽  
Power Diodes ◽  
Bias Stress

Improved Characteristics of SiC MOSFETs by Post-Oxidation Annealing in Ar at High Temperature

2011 ◽  
Vol 679-680 ◽  
pp. 445-448 ◽  
Author(s):  
Muneharu Kato ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
High Temperature ◽  
Thermal Oxidation ◽  
Field Effect ◽  
Secondary Ion Mass Spectrometry ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Gate Oxides ◽  
Secondary Ion ◽  
Improved Characteristics ◽  
Peak Value

Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Reverse bias instabilities in bipolar power transistors with cellular layout

2001 ◽  
Vol 48 (11) ◽  
pp. 2544-2550 ◽  
Author(s):  
G. Busatto ◽  
L. Fratelli ◽  
G. Vitale
Keyword(s):  
Reverse Bias ◽  
Power Transistors ◽  
Cellular Layout
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