Negative Bias Temperature Instability Characteristics and Degradation Mechanisms of pMOSFET with High-k/Metal Gate Stacks

2013 ◽  
Vol 52 (1) ◽  
pp. 953-957 ◽  
Author(s):  
S. Ren ◽  
H. Yang ◽  
W. Wang ◽  
H. Xu ◽  
W. Luo ◽  
...  
Keyword(s):  
Negative Bias ◽  
Degradation Mechanisms ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Metal Gate ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High K

Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs

2013 ◽  
Vol 53 (9-11) ◽  
pp. 1351-1354
Author(s):  
Seonhaeng Lee ◽  
Cheolgyu Kim ◽  
Hyeokjin Kim ◽  
Gang-Jun Kim ◽  
Ji-Hoon Seo ◽  
...  
Keyword(s):  
Negative Bias ◽  
Negative Bias Temperature Instability ◽  
Metal Gate ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High K ◽  
Stress Voltage

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

2007 ◽  
Vol 17 (01) ◽  
pp. 129-141
Author(s):  
N. A. CHOWDHURY ◽  
D. MISRA ◽  
N. RAHIM
Keyword(s):  
Interface State ◽  
Initial Time ◽  
Negative Bias ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High Bias ◽  
The Impact

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

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