On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices

2003 ◽  
Author(s):  
D. Goren ◽  
R. Groves ◽  
J. Park ◽  
D. Jordan ◽  
S. Strang ◽  
...  
Keyword(s):  
Transmission Line ◽  
Modeling Methodology ◽  
High Bandwidth ◽  
On Chip

On-chip interconnect-aware design and modeling methodology based on high bandwidth transmission line devices

2004 ◽  
Author(s):  
D. Goren ◽  
M. Zelikson ◽  
R. Gordin ◽  
I.A. Wagner ◽  
A. Barger ◽  
...  
Keyword(s):  
Transmission Line ◽  
Modeling Methodology ◽  
High Bandwidth ◽  
On Chip

scholarly journals A Latency-Optimized Network-on-Chip with Rapid Bypass Channels

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 621
Author(s):  
Wenheng Ma ◽  
Xiyao Gao ◽  
Yudi Gao ◽  
Ningmei Yu
Keyword(s):  
Great Reduction ◽  
Network On Chip ◽  
Traffic Patterns ◽  
Single Cycle ◽  
High Bandwidth ◽  
On Chip

Network-on-Chips with simple topologies are widely used due to their scalability and high bandwidth. The transmission latency increases greatly with the number of on-chip nodes. A NoC, called single-cycle multi-hop asynchronous repeated traversal (SMART), is proposed to solve the problem by bypassing intermediate routers. However, the bypass setup request of SMART requires additional pipeline stages and wires. In this paper, we present a NoC with rapid bypass channels that integrates the bypass information into each flit. In the proposed NoC, all the bypass requests are delivered along with flits at the same time reducing the transmission latency. Besides, the bypass request is unicasted in our design instead of broadcasting in SMART leading to a great reduction in wire overhead. We evaluate the NoC in four synthetic traffic patterns. The result shows that the latency of our proposed NoC is 63.54% less than the 1-cycle NoC. Compared to SMART, more than 80% wire overhead and 27% latency are reduced.

scholarly journals High bandwidth on-chip capacitive tuning of microtoroid resonators

2016 ◽  
Vol 24 (18) ◽  
pp. 20400 ◽  
Author(s):  
Christopher G. Baker ◽  
Christiaan Bekker ◽  
David L. McAuslan ◽  
Eoin Sheridan ◽  
Warwick P. Bowen
Keyword(s):  
High Bandwidth ◽  
Capacitive Tuning ◽  
On Chip

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

Thermomechanical Interaction Between Thin Bare-Die Package and Thermal Solution in Next-Generation Mobile Computing Platforms

2019 ◽  
Vol 141 (1) ◽  
Author(s):  
Aastha Uppal ◽  
Jerrod Peterson ◽  
Je-Young Chang ◽  
Xi Guo ◽  
Frank Liang ◽  
...  
Keyword(s):  
Design Parameters ◽  
Next Generation ◽  
Mobile Platforms ◽  
Robust Modeling ◽  
Modeling Methodology ◽  
Bga Packages ◽  
Thermal Solution ◽  
Computing Platforms ◽  
And Performance ◽  
On Chip

The demands for both thinner bare-die ball grid array (BGA) packages and thinner thermal solutions have added complexity for the thermal enabling design and material options associated with system on chip packages in mobile personal computer (PC) platforms. The thermomechanical interactions between the bare-die package and the thermal solution are very critical, creating the needs for: (1) an in-depth thermomechanical characterization to understand their impacts on product quality and performance and (2) a simple and yet robust modeling methodology to analyze design parameters using a commercially available software. In this paper, experimental metrologies and modeling methodology are developed with the details of contents documented. Validation of the newly developed tools and recommendation/guidance are also discussed for detailed assessments of thermomechanical tradeoffs for optimal design spaces for next-generation mobile platforms.

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