Thermomechanical Interaction Between Thin Bare-Die Package and Thermal Solution in Next-Generation Mobile Computing Platforms

2019 ◽  
Vol 141 (1) ◽  
Author(s):  
Aastha Uppal ◽  
Jerrod Peterson ◽  
Je-Young Chang ◽  
Xi Guo ◽  
Frank Liang ◽  
...  
Keyword(s):  
Design Parameters ◽  
Next Generation ◽  
Mobile Platforms ◽  
Robust Modeling ◽  
Modeling Methodology ◽  
Bga Packages ◽  
Thermal Solution ◽  
Computing Platforms ◽  
And Performance ◽  
On Chip

The demands for both thinner bare-die ball grid array (BGA) packages and thinner thermal solutions have added complexity for the thermal enabling design and material options associated with system on chip packages in mobile personal computer (PC) platforms. The thermomechanical interactions between the bare-die package and the thermal solution are very critical, creating the needs for: (1) an in-depth thermomechanical characterization to understand their impacts on product quality and performance and (2) a simple and yet robust modeling methodology to analyze design parameters using a commercially available software. In this paper, experimental metrologies and modeling methodology are developed with the details of contents documented. Validation of the newly developed tools and recommendation/guidance are also discussed for detailed assessments of thermomechanical tradeoffs for optimal design spaces for next-generation mobile platforms.

Hybrid-model-based stiffness analysis of a three-revolute-prismatic-spherical parallel kinematic machine

2016 ◽  
Vol 231 (14) ◽  
pp. 2561-2576 ◽  
Author(s):  
Jun Zhang ◽  
Yan Q Zhao ◽  
Hai W Luo
Keyword(s):  
High Speed ◽  
Experimental Tests ◽  
Design Parameters ◽  
Parallel Kinematic Machine ◽  
Modeling Methodology ◽  
Parallel Kinematic ◽  
Stiffness Characteristics ◽  
And Performance ◽  
High Dynamics ◽  
Spring Constants

A three-revolute-prismatic-spherical parallel kinematic machine is proposed as an alternative solution for high-speed machining tool due to its high rigidity and high dynamics. Considering the parallel kinematic machine module as a typical compliant parallel mechanism, whose three limb assemblages have bending, extending and torsional deflections, this article proposes a hybrid modeling methodology to establish an analytical stiffness model for the three-revolute-prismatic-spherical device. The developed analytical model is further used to evaluate the stiffness mapping of the three-revolute-prismatic-spherical module over a given work plane which is then validated by experimental tests. The simulations and experiments indicate that the present hybrid methodology can predict the three-revolute-prismatic-spherical parallel kinematic machine’s stiffness in a quick and accurate manner. The solution for eigenvalue problem of the stiffness matrix leads to the stiffness characteristics of the parallel module including eigenstiffnesses and the corresponding eigenscrews as well as the equivalent screw spring constants. Based on the eigenscrew decomposition, the parallel kinematic machine is physically interpreted as a rigid platform suspending by six screw springs. The minimum, maximum and average of the screw spring constants are chosen as indices to assess the three-revolute-prismatic-spherical parallel kinematic machine’s stiffness performance. The distributions of the proposed indices throughout the workspace reveal a strong dependency on the mechanism’s configurations. At the final stage, the effects of some design parameters on system stiffness characteristics are investigated with the purpose of providing useful information for the conceptual design and performance improvement of the parallel kinematic machine.

scholarly journals A modular design method based on TRIZ and AD and its application to cutter changing robot

2021 ◽  
Vol 13 (7) ◽  
pp. 168781402110343
Author(s):  
Mei Yang ◽  
Yimin Xia ◽  
Lianhui Jia ◽  
Dujuan Wang ◽  
Zhiyong Ji
Keyword(s):  
Modular Design ◽  
Design Method ◽  
Idea Generation ◽  
Design Parameters ◽  
Problem Analysis ◽  
Concept Design ◽  
Functional Requirements ◽  
Shield Tunneling ◽  
Structural Hierarchy ◽  
And Performance

Modular design, Axiomatic design (AD) and Theory of inventive problem solving (TRIZ) have been increasingly popularized in concept design of modern mechanical product. Each method has their own advantages and drawbacks. The benefit of modular design is reducing the product design period, and AD has the capability of problem analysis, while TRIZ’s expertise is innovative idea generation. According to the complementarity of these three approaches, an innovative and systematic methodology is proposed to design big complex mechanical system. Firstly, the module partition is executed based on scenario decomposition. Then, the behavior attributes of modules are listed to find the design contradiction, including motion form, spatial constraints, and performance requirements. TRIZ tools are employed to deal with the contradictions between behavior attributes. The decomposition and mapping of functional requirements and design parameters are carried out to construct the structural hierarchy of each module. Then, modules are integrated considering the connections between each other. Finally, the operation steps in application scenario are designed in temporal and spatial dimensions. Design of cutter changing robot for shield tunneling machine is taken as an example to validate the feasibility and effectiveness of the proposed method.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

Econometrics Pedagogy and Cloud Computing: Training the Next Generation of Economists and Data Scientists

2020 ◽  
Vol 0 (0) ◽  
Author(s):  
Danielle V. Handel ◽  
Anson T. Y. Ho ◽  
Kim P. Huynh ◽  
David T. Jacho-Chávez ◽  
Carson H. Rea
Keyword(s):  
Cloud Computing ◽  
Data Science ◽  
Internet Access ◽  
Next Generation ◽  
Web Browser ◽  
Computer Laboratory ◽  
Economics Students ◽  
Computing Platforms

AbstractThis paper describes how cloud computing tools widely used in the instruction of data scientists can be introduced and taught to economics students as part of their curriculum. The demonstration centers around a workflow where the instructor creates a virtual server and the students only need Internet access and a web browser to complete in-class tutorials, assignments, or exams. Given how prevalent cloud computing platforms are becoming for data science, introducing these techniques into students’ econometrics training would prepare them to be more competitive when job hunting, while making instructors and administrators re-think what a computer laboratory means on campus.

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

Implementing the Mechanistic–Empirical Design Guide Procedure for a Hot-Mix Asphalt–Rehabilitated Pavement in Indiana

2005 ◽  
Vol 1919 (1) ◽  
pp. 121-133 ◽  
Author(s):  
Khaled A. Galal ◽  
Ghassan R. Chehab
Keyword(s):  
Hot Mix Asphalt ◽  
Pavement Design ◽  
Design Parameters ◽  
Design Procedures ◽  
Design Concepts ◽  
Asphalt Overlay ◽  
Design Guide ◽  
Strategic Goals ◽  
And Performance

One of the Indiana Department of Transportation's (INDOT's) strategic goals is to improve its pavement design procedures. This goal can be accomplished by fully implementing the 2002 mechanistic–empirical (M-E) pavement design guide (M-E PDG) once it is approved by AASHTO. The release of the M-E PDG software has provided a unique opportunity for INDOT engineers to evaluate, calibrate, and validate the new M-E design process. A continuously reinforced concrete pavement on I-65 was rubblized and overlaid with a 13–in.-thick hot-mix asphalt overlay in 1994. The availability of the structural design, material properties, and climatic and traffic conditions, in addition to the availability of performance data, provided a unique opportunity for comparing the predicted performance of this section using the M-E procedure with the in situ performance; calibration efforts were conducted subsequently. The 1993 design of this pavement section was compared with the 2002 M-E design, and performance was predicted with the same design inputs. In addition, design levels and inputs were varied to achieve the following: ( a) assess the functionality of the M-E PDG software and the feasibility of applying M-E design concepts for structural pavement design of Indiana roadways, ( b) determine the sensitivity of the design parameters and the input levels most critical to the M-E PDG predicted distresses and their impact on the implementation strategy that would be recommended to INDOT, and ( c) evaluate the rubblization technique that was implemented on the I-65 pavement section.

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