Low-energy off-chip SDRAM memory systems for embedded applications

2003 ◽  
Vol 2 (1) ◽  
pp. 98-130 ◽  
Author(s):  
Hojun Shim ◽  
Yongsoo Joo ◽  
Yongseok Choi ◽  
Hyung Gyu Lee ◽  
Naehyuck Chang
2019 ◽  
Vol 29 (09) ◽  
pp. 2050135
Author(s):  
Hassan Salamy

Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.


Author(s):  
Tohru Ishihara ◽  
Seiichiro Yamaguchi ◽  
Yuriko Ishitobi ◽  
Tadayuki Matsumura ◽  
Yuji Kunitake ◽  
...  

2017 ◽  
Vol 7 (1.5) ◽  
pp. 285
Author(s):  
Jenitha A ◽  
Elumalai R

Memory systems in many applications are becoming increasingly large, contributing to many challenges in the memory management that has led to many method to manage memory. The tag comparison consumes large amount of cache energy. Current methods provide tag comparison cache or failure of the expected cache. Here is proposed an idea based on new call Comparing Tag stages, filter bloom is presented to improve the efficiency of the cache to predict failure and partial tag comparison for the cold line of verification and full comparison check for direct labels. Moreover, the administration of the cache that is filled with cache lines occurs when there is a cache miss. Today's embedded applications use MPSoC. The  MPSoC consists of the following ie more than one  processors, shared memory among the processors available and a global  off-chip memory. Planning of the activities of an integrated application processor and memory partition between processors are two main critical problem. Here, for an integrated application, both task scheduling and partitioning the integrated available L2 cache to reduce the runtime approach is used.


2009 ◽  
Vol 2 ◽  
pp. 239-249
Author(s):  
Tadayuki Matsumura ◽  
Tohru Ishihara ◽  
Hiroto Yasuura

2016 ◽  
Vol 39 ◽  
Author(s):  
Giosuè Baggio ◽  
Carmelo M. Vicario

AbstractWe agree with Christiansen & Chater (C&C) that language processing and acquisition are tightly constrained by the limits of sensory and memory systems. However, the human brain supports a range of cognitive functions that mitigate the effects of information processing bottlenecks. The language system is partly organised around these moderating factors, not just around restrictions on storage and computation.


Author(s):  
A. Garg ◽  
W.A.T. Clark ◽  
J.P. Hirth

In the last twenty years, a significant amount of work has been done in the theoretical understanding of grain boundaries. The various proposed grain boundary models suggest the existence of coincidence site lattice (CSL) boundaries at specific misorientations where a periodic structure representing a local minimum of energy exists between the two crystals. In general, the boundary energy depends not only upon the density of CSL sites but also upon the boundary plane, so that different facets of the same boundary have different energy. Here we describe TEM observations of the dissociation of a Σ=27 boundary in silicon in order to reduce its surface energy and attain a low energy configuration.The boundary was identified as near CSL Σ=27 {255} having a misorientation of (38.7±0.2)°/[011] by standard Kikuchi pattern, electron diffraction and trace analysis techniques. Although the boundary appeared planar, in the TEM it was found to be dissociated in some regions into a Σ=3 {111} and a Σ=9 {122} boundary, as shown in Fig. 1.


Author(s):  
G. G. Hembree ◽  
Luo Chuan Hong ◽  
P.A. Bennett ◽  
J.A. Venables

A new field emission scanning transmission electron microscope has been constructed for the NSF HREM facility at Arizona State University. The microscope is to be used for studies of surfaces, and incorporates several surface-related features, including provision for analysis of secondary and Auger electrons; these electrons are collected through the objective lens from either side of the sample, using the parallelizing action of the magnetic field. This collimates all the low energy electrons, which spiral in the high magnetic field. Given an initial field Bi∼1T, and a final (parallelizing) field Bf∼0.01T, all electrons emerge into a cone of semi-angle θf≤6°. The main practical problem in the way of using this well collimated beam of low energy (0-2keV) electrons is that it is travelling along the path of the (100keV) probing electron beam. To collect and analyze them, they must be deflected off the beam path with minimal effect on the probe position.


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