Power reduction by simultaneous voltage scaling and gate sizing

2000 ◽  
Author(s):  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Voltage Scaling ◽  
Power Reduction ◽  
Gate Sizing

scholarly journals Power Optimization of Delay Constrained Circuits

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 125-138
Author(s):  
Anshuman Nayak ◽  
Malay Haldar ◽  
Prith Banerjee ◽  
Chunhong Chen ◽  
Majid Sarrafzadeh
Keyword(s):  
Power Dissipation ◽  
Short Circuit ◽  
Average Power ◽  
Accurate Estimate ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Total Power ◽  
Gate Sizing ◽  
Dynamic Power ◽  
Circuit Power

We present a framework for combining Voltage Scaling (VS) and Gate Sizing (GS) techniques for power optimizations. We introduce a fast heuristic for choosing gates for sizing and voltage scaling such that the total power is minimized under delay constraints. We also use a more accurate estimate for determining the power dissipation of the circuit by taking into account the short circuit power along with the dynamic power. A better model of the short circuit power is used which takes into account the load capacitance of the gates. Our results show that the combination of VS and GS perform better than the techniques applied in isolation. An average power reduction of 73% is obtained when decisions are taken assuming dynamic power only. In contrast, average power reduction is 77% when decisons include the short circuit power dissipation.

A gate sizing method for glitch power reduction

2011 ◽  
Author(s):  
L. Wang ◽  
M. Olbrich ◽  
E. Barke ◽  
T. Buchner ◽  
M. Buhler ◽  
...  
Keyword(s):  
Power Reduction ◽  
Gate Sizing

Low Power Devnagari Unicode Checker Design Using CGVS Approach

2014 ◽  
Vol 984-985 ◽  
pp. 1282-1285
Author(s):  
S.M. Mohaiminul Islam ◽  
Mahbub E. Noor ◽  
Bishwajeet Pandey ◽  
Tanesh Kumar ◽  
Md Atiqur Rahman ◽  
...  
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Power Reduction ◽  
Clock Gating ◽  
New Approach ◽  
Speed Grade

In this paper we have introduced a new approach called Clock Gating and Voltage Scaling (CGVS), which is the combination of two existing techniques i.e. Clock gating and Voltage Scaling. Our aim is to design a low power Devnagari Unicode Checker (DUC) using CGVS technique. This design is implemented on Kintex-7 FPGA families, XC7K70T device, -3 speed grade and FBG676 package. From our analysis, it is observed that, with the use of clock gated technique in our target circuit and with the scaling of voltage from 1.0V to 0.1V, we are achieving clock power reduction of 98.98% on 10GHz and 1THz operating frequencies. Under same voltage scaling scheme, there is 6.66%, 10.38%, 10.64% and 10.62% less reduction in IO power, when the target circuit is operating on 1GHz, 10GHz, 100GHz and 1THz operating frequencies.

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