Dynamic Buffer Sizing for Out-of-order Event Compensation for Time-sensitive Applications

Wolfgang Weiss; Víctor J. Expósito Jiménez; Herwig Zeiner

doi:10.1145/3410403

Dynamic Buffer Sizing for Out-of-order Event Compensation for Time-sensitive Applications

ACM Transactions on Sensor Networks ◽

10.1145/3410403 ◽

2020 ◽

Vol 17 (1) ◽

pp. 1-23

Author(s):

Wolfgang Weiss ◽

Víctor J. Expósito Jiménez ◽

Herwig Zeiner

Keyword(s):

Buffer Sizing

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Buffer Sizing in Internet Routers

Journal of Software ◽

10.3724/sp.j.1001.2008.00733 ◽

2008 ◽

Vol 19 (3) ◽

pp. 733-743

Author(s):

Yu-Feng LI

Keyword(s):

Internet Routers ◽

Buffer Sizing

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Proceedings of the 2019 Workshop on Buffer Sizing

10.1145/3375235 ◽

2019 ◽

Keyword(s):

Buffer Sizing

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Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew

Proceedings of the 24th Asia and South Pacific Design Automation Conference on - ASPDAC '19 ◽

10.1145/3287624.3287681 ◽

2019 ◽

Author(s):

Necati Uysal ◽

Wen-Hao Liu ◽

Rickard Ewetz

Keyword(s):

Buffer Sizing ◽

Layer Assignment

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Mathematical analysis of buffer sizing for Network-on-Chips under multimedia traffic

2008 IEEE International Conference on Computer Design ◽

10.1109/iccd.2008.4751854 ◽

2008 ◽

Cited By ~ 2

Author(s):

Ahmad Khonsari ◽

Mohammad R. Aghajani ◽

Arash Tavakkol ◽

Mohammad S. Talebi

Keyword(s):

Mathematical Analysis ◽

Multimedia Traffic ◽

Buffer Sizing

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Data-driven project buffer sizing in critical chains

Automation in Construction ◽

10.1016/j.autcon.2022.104134 ◽

2022 ◽

Vol 135 ◽

pp. 104134

Author(s):

Hongbo Li ◽

Yiwu Cao ◽

Qiao Lin ◽

Hanyu Zhu

Keyword(s):

Data Driven ◽

Buffer Sizing

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Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014 ◽

10.7873/date2014.276 ◽

2014 ◽

Cited By ~ 1

Author(s):

Kitae Park ◽

Geunho Kim ◽

Taewhan Kim

Keyword(s):

Clock Tree ◽

Buffer Sizing ◽

Clock Tree Synthesis ◽

Power Mode ◽

Multiple Power ◽

Tree Synthesis

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Buffer Sizing Method of CCPM Technique Using Statistical Analysis

The Journal of the Korea Contents Association ◽

10.5392/jkca.2012.12.08.029 ◽

2012 ◽

Vol 12 (8) ◽

pp. 29-36 ◽

Cited By ~ 1

Author(s):

Jing-Chao Liu ◽

Taeg-Keun WhangBo

Keyword(s):

Statistical Analysis ◽

Buffer Sizing

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BUFFER SIZING FOR THE CRITICAL CHAIN PROJECT MANAGEMENT METHOD

The South African Journal of Industrial Engineering ◽

10.7166/19-1-107 ◽

2012 ◽

Vol 19 (1) ◽

Cited By ~ 1

Author(s):

A. Geekie ◽

H. Steyn

Keyword(s):

Project Management ◽

Buffer Sizing ◽

Critical Chain Project Management ◽

Management Method ◽

Critical Chain

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Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2013.2293067 ◽

2014 ◽

Vol 33 (4) ◽

pp. 532-545 ◽

Cited By ~ 4

Author(s):

Logan Rakai ◽

Amin Farshidi ◽

David Westwick ◽

Laleh Behjat

Keyword(s):

Geometric Programming ◽

Programming Models ◽

Clock Network ◽

Buffer Sizing ◽

Network Buffer

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Machine buffer sizing based on the theory of constraint principles and the tabu search technique

Proceedings of the Institution of Mechanical Engineers Part B Journal of Engineering Manufacture ◽

10.1177/095440540421801214 ◽

2004 ◽

Vol 218 (12) ◽

pp. 1825-1832 ◽

Cited By ~ 1

Author(s):

S Apolloni ◽

M Lando ◽

M Savino

Keyword(s):

Tabu Search ◽

Search Technique ◽

Buffer Sizing ◽

Theory Of Constraint

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