High Level Synthesis Based Hardware Accelerator Design for Processing SQL Queries

2015 ◽  
Author(s):  
Gorker Alp Malazgirt ◽  
Nehir Sonmez ◽  
Arda Yurdakul ◽  
Adrian Cristal ◽  
Osman Unsal
Keyword(s):  
High Level Synthesis ◽  
Hardware Accelerator ◽  
High Level ◽  
Accelerator Design

scholarly journals SVM-based switching filter hardware design for mixed noise reduction in digital images using high-level synthesis tools

2022 ◽  
Vol 12 (1) ◽  
pp. 0-0
Keyword(s):  
Image Quality ◽  
Support Vector Machine Classifier ◽  
Digital Images ◽  
High Level Synthesis ◽  
Support Vector ◽  
Hardware Accelerator ◽  
Mixed Noise ◽  
High Level ◽  
Switching Filter ◽  
Better Than

Impulse and Gaussian are the two most common types of noise that affect digital images due to imperfections in the imaging process, compression, storage and communication. The conventional filtering approaches, however, reduce the image quality in terms of sharpness and resolution while suppressing the effects of noise. In this work, a machine learning-based filtering structure has been proposed preserves the image quality while effectively removing the noise. Specifically, a support vector machine classifier is employed to detect the type of noise affecting each pixel to select an appropriate filter. The choice of filters includes Median and Bilateral filters of different kernel sizes. The classifier is trained using example images with known noise parameters. The proposed filtering structure has been shown to perform better than the conventional approaches in terms of image quality metrics. Moreover, the design has been implemented as a hardware accelerator on an FPGA device using high-level synthesis tools.

scholarly journals High-Level Synthesis of Online K-Means Clustering Hardware for a Real-Time Image Processing Pipeline

2019 ◽  
Vol 5 (3) ◽  
pp. 38 ◽  
Author(s):  
Aiman Badawi ◽  
Muhammad Bilal
Keyword(s):  
Image Processing ◽  
Image Segmentation ◽  
Real Time ◽  
Moving Average ◽  
Weighted Average ◽  
High Level Synthesis ◽  
Hardware Accelerator ◽  
Hardware Complexity ◽  
Processing Pipeline ◽  
High Level

The growing need for smart surveillance solutions requires that modern video capturing devices to be equipped with advance features, such as object detection, scene characterization, and event detection, etc. Image segmentation into various connected regions is a vital pre-processing step in these and other advanced computer vision algorithms. Thus, the inclusion of a hardware accelerator for this task in the conventional image processing pipeline inevitably reduces the workload for more advanced operations downstream. Moreover, design entry by using high-level synthesis tools is gaining popularity for the facilitation of system development under a rapid prototyping paradigm. To address these design requirements, we have developed a hardware accelerator for image segmentation, based on an online K-Means algorithm using a Simulink high-level synthesis tool. The developed hardware uses a standard pixel streaming protocol, and it can be readily inserted into any image processing pipeline as an Intellectual Property (IP) core on a Field Programmable Gate Array (FPGA). Furthermore, the proposed design reduces the hardware complexity of the conventional architectures by employing a weighted instead of a moving average to update the clusters. Experimental evidence has also been provided to demonstrate that the proposed weighted average-based approach yields better results than the conventional moving average on test video sequences. The synthesized hardware has been tested in real-time environment to process Full HD video at 26.5 fps, while the estimated dynamic power consumption is less than 90 mW on the Xilinx Zynq-7000 SOC.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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