Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines

2015 ◽  
Vol 20 (4) ◽  
pp. 1-32 ◽  
Author(s):  
Ingoo Heo ◽  
Minsu Kim ◽  
Yongje Lee ◽  
Changho Choi ◽  
Jinyong Lee ◽  
...  
Keyword(s):  
Program Analysis ◽  
Dynamic Program ◽  
System Level ◽  
Instruction Set ◽  
Specific Instruction ◽  
Dynamic Program Analysis ◽  
Application Specific

scholarly journals System Level Modeling Methodology of Application Specific Instruction Set Processor (SIP) Using SystemC

1970 ◽  
Vol 7 (1) ◽  
pp. 44-49 ◽  
Author(s):  
Rana Mukherji ◽  
Manishita Das
Keyword(s):  
System Integration ◽  
Speech Synthesis ◽  
System Level ◽  
Instruction Set ◽  
Specific Instruction ◽  
Modeling Methodology ◽  
Hardware Description ◽  
Natural Solution ◽  
Description Languages ◽  
Application Specific

In recent years, the development of application specific instruction set processors (ASIP) is the exclusive domain of the semiconductor houses and core vendors. This is due to the fact that constructing such architecture is a difficult assignment that needs skilled knowledge in distinct domains: application software development tools, processor hardware implementation, and system integration and verification. To specify the design and implementation of such systems and incorporate the functionality implemented in both hardware and software forms, we are compelled to move on from traditional Hardware Description Languages (HDLs). Since C and C++ are dominant languages used by chip architects, system engineers and software engineers today, we believe that a C++ based approach to hardware modeling is necessary. This will enable codesign, providing a more natural solution to partitioning fuctionality between hardware and software. In this paper, we discuss a design approach of SystemC (a C++ class library) for ASIP at the system-level which provides necessary features for modeling design hierarchy, concurrency and reactivity in hardware. To exemplify and validate the method we employed it to the design of a 32-bit ASIP for Hindi Text-to-Speech Synthesis developed by CEERI, Pilani (INDIA). Keywords: ASIP; System; System Level Design   DOI: http://dx.doi.org/10.3329/diujst.v7i1.9647 Daffodil International University Journal of Science and Technology Vol.7(1) 2012 44-49

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors

2017 ◽  
Vol 66 (4) ◽  
pp. 647-660 ◽  
Author(s):  
Tuo Li ◽  
Muhammad Shafique ◽  
Jude Angelo Ambrose ◽  
Jorg Henkel ◽  
Sri Parameswaran
Keyword(s):  
Instruction Set ◽  
Specific Instruction ◽  
Fine Grained ◽  
Checkpoint Recovery ◽  
Instruction Set Processors ◽  
Application Specific

scholarly journals An Optimization Methodology for Adapting Legacy SGX Applications to Use Switchless Calls

2021 ◽  
Vol 11 (18) ◽  
pp. 8379
Author(s):  
Seongmin Kim
Keyword(s):  
System Level ◽  
Instruction Set ◽  
Optimization Strategy ◽  
Design Decisions ◽  
Systematic Analysis ◽  
Kernel Module ◽  
Recent Innovation ◽  
Optimization Methodology ◽  
Application Specific ◽  
Trusted Execution Environment

A recent innovation in the trusted execution environment (TEE) technologies enables the delegation of privacy-preserving computation to the cloud system. In particular, Intel SGX, an extension of x86 instruction set architecture (ISA), accelerates this trend by offering hardware-protected isolation with near-native performance. However, SGX inherently suffers from performance degradation depending on the workload characteristics due to the hardware restriction and design decisions that primarily concern the security guarantee. The system-level optimizations on SGX runtime and kernel module have been proposed to resolve this, but they cannot effectively reflect application-specific characteristics that largely impact the performance of legacy SGX applications. This work presents an optimization strategy to achieve application-level optimization by utilizing asynchronous switchless calls to reduce enclave transition, one of the dominant overheads of using SGX. Based on the systematic analysis, our methodology examines the performance benefit for each enclave transition wrapper and selectively applies switchless calls without modifying the legacy codebases. The evaluation shows that our optimization strategy successfully improves the end-to-end performance of our showcasing application, an SGX-enabled network middlebox.

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