Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

Zhibin Liang; Wei Zhang; Yung-Cheng Ma

doi:10.1145/2632218

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

ACM Transactions on Architecture and Code Optimization ◽

10.1145/2632218 ◽

2014 ◽

Vol 11 (2) ◽

pp. 1-26 ◽

Cited By ~ 2

Author(s):

Zhibin Liang ◽

Wei Zhang ◽

Yung-Cheng Ma

Keyword(s):

Vliw Architectures

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Loop fusion for clustered VLIW architectures

Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02 ◽

10.1145/513829.513850 ◽

2002 ◽

Cited By ~ 9

Author(s):

Yi Qian ◽

Steve Carr ◽

Philip Sweany

Keyword(s):

Loop Fusion ◽

Vliw Architectures

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A compiler optimization to reduce soft errors in register files

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09 ◽

10.1145/1542452.1542459 ◽

2009 ◽

Cited By ~ 11

Author(s):

Jongeun Lee ◽

Aviral Shrivastava

Keyword(s):

Compiler Optimization ◽

Soft Errors ◽

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Code scheduling for VLIW/superscalar processors with limited register files

ACM SIGMICRO Newsletter ◽

10.1145/144965.145802 ◽

1992 ◽

Vol 23 (1-2) ◽

pp. 197-201

Author(s):

Tokuzo Kiyohara ◽

John C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Code Scheduling

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Area and Timing Estimation in Register Files Using Neural Networks

Circuits and Systems ◽

10.4236/cs.2012.33037 ◽

2012 ◽

Vol 03 (03) ◽

pp. 269-277

Author(s):

Assim Sagahyroon ◽

Jamal Abdalla

Keyword(s):

Neural Networks ◽

Timing Estimation ◽

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An instruction-level energy model for embedded VLIW architectures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2002.801105 ◽

2002 ◽

Vol 21 (9) ◽

pp. 998-1010 ◽

Cited By ~ 24

Author(s):

M. Sami ◽

D. Sciuto ◽

C. Silvano ◽

V. Zaccaria

Keyword(s):

Energy Model ◽

Level Energy ◽

Vliw Architectures

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Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

2006 49th IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2006.382112 ◽

2006 ◽

Cited By ~ 16

Author(s):

Riaz Naseer ◽

Rashed Zafar Bhatti ◽

Jeff Draper

Keyword(s):

Soft Error ◽

Error Mitigation ◽

Mitigation Techniques ◽

Soft Error Mitigation

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Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures

Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01 ◽

10.1145/502217.502241 ◽

2001 ◽

Cited By ~ 5

Author(s):

Marcio Buss ◽

Rodolfo Azevedo ◽

Paulo Centoducatte ◽

Guido Araujo

Keyword(s):

Functional Unit ◽

Vliw Architectures

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Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance

Communications in Computer and Information Science - Computer and Information Sciences ◽

10.1007/978-3-030-00840-6_5 ◽

2018 ◽

pp. 41-48

Author(s):

Hasancan Güngörer ◽

Gürhan Küçük

Keyword(s):

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Low power register files by eliminating redundant read

IEICE Electronics Express ◽

10.1587/elex.11.20140774 ◽

2014 ◽

Vol 11 (18) ◽

pp. 20140774-20140774

Author(s):

Leiou Wang ◽

Donghui Wang ◽

Huan Ying ◽

Chengpeng Hao

Keyword(s):

Low Power ◽

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Early Register Deallocation Mechanisms Using Checkpointed Register Files

IEEE Transactions on Computers ◽

10.1109/tc.2006.145 ◽

2006 ◽

Vol 55 (9) ◽

pp. 1153-1166 ◽

Cited By ~ 13

Author(s):

O. Ergin ◽

D. Balkan ◽

D. Ponomarev ◽

K. Ghose

Keyword(s):

Download Full-text