Feedback, correlation, and delay concerns in the power estimation of VLSI circuits

1995 ◽  
Author(s):  
Farid N. Najm
Keyword(s):  
Power Estimation ◽  
Vlsi Circuits

MAXIMUM POWER ESTIMATION IN CMOS VLSI CIRCUITS

2001 ◽  
Author(s):  
N. E. EVMORFOPOULOS ◽  
J. N. AVARITSIOTIS ◽  
G. I. STAMOULIS
Keyword(s):  
Power Estimation ◽  
Vlsi Circuits ◽  
Maximum Power ◽  
Cmos Vlsi

Peak power estimation of VLSI circuits: new peak power measures

2000 ◽  
Vol 8 (4) ◽  
pp. 435-439 ◽  
Author(s):  
M.S. Hsiao ◽  
E.M. Rudnick ◽  
J.H. Patel
Keyword(s):  
Peak Power ◽  
Power Estimation ◽  
Vlsi Circuits

scholarly journals Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

VLSI Design ◽  
2002 ◽  
Vol 15 (1) ◽  
pp. 407-416 ◽  
Author(s):  
Michael S. Hsiao
Keyword(s):  
Peak Power ◽  
Power Estimation ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Experimental Results ◽  
Switching Function ◽  
Circuit Delay ◽  
Optimization Heuristics ◽  
Multiple Switching ◽  
Output Capacitance

Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

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