Peak power estimation of VLSI circuits: new peak power measures

M.S. Hsiao; E.M. Rudnick; J.H. Patel

doi:10.1109/92.863624

Peak power estimation of VLSI circuits: new peak power measures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.863624 ◽

2000 ◽

Vol 8 (4) ◽

pp. 435-439 ◽

Cited By ~ 19

Author(s):

M.S. Hsiao ◽

E.M. Rudnick ◽

J.H. Patel

Keyword(s):

Peak Power ◽

Power Estimation ◽

Vlsi Circuits

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Peak power estimation using genetic spot optimization for large VLSI circuits

Proceedings of the conference on Design, automation and test in Europe - DATE '99 ◽

10.1145/307418.307484 ◽

1999 ◽

Cited By ~ 9

Author(s):

Michael S. Hsiao

Keyword(s):

Peak Power ◽

Power Estimation ◽

Vlsi Circuits

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A novel ACO-based pattern generation for peak power estimation in VLSI circuits

2009 10th International Symposium on Quality of Electronic Design ◽

10.1109/isqed.2009.4810314 ◽

2009 ◽

Author(s):

Yi-Ling Liu ◽

Chun-Yao Wang ◽

Yung-Chih Chen ◽

Ya-Hsin Chang

Keyword(s):

Peak Power ◽

Power Estimation ◽

Pattern Generation ◽

Vlsi Circuits

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Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

VLSI Design ◽

10.1080/1065514021000012020 ◽

2002 ◽

Vol 15 (1) ◽

pp. 407-416 ◽

Cited By ~ 1

Author(s):

Michael S. Hsiao

Keyword(s):

Peak Power ◽

Power Estimation ◽

Sequential Circuits ◽

Vlsi Circuits ◽

Experimental Results ◽

Switching Function ◽

Circuit Delay ◽

Optimization Heuristics ◽

Multiple Switching ◽

Output Capacitance

Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP) of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.

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