On nominal delay minimization in LUT-based FPGA technology mapping

Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays - FPGA '95 ◽

10.1145/201310.201324 ◽

1995 ◽

Author(s):

Jason Cong ◽

Yuzheng Ding

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Combining technology mapping and placement for delay-minimization in FPGA designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.406709 ◽

1995 ◽

Vol 14 (9) ◽

pp. 1076-1084 ◽

Cited By ~ 1

Author(s):

Chau-Shen Chen ◽

Yu-Wen Tsay ◽

TingTing Hwang ◽

A.C.H. Wu ◽

Youn-Long Lin

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Simultaneous Technology Mapping and Placement for Delay Minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2089569 ◽

2011 ◽

Vol 30 (3) ◽

pp. 416-426 ◽

Cited By ~ 3

Author(s):

Yifang Liu ◽

Rupesh S. Shelar ◽

Jiang Hu

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840284 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Ciric ◽

G. Yee ◽

C. Sechen

Keyword(s):

Technology Mapping ◽

Domino Logic ◽

Delay Minimization

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Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343781 ◽

2000 ◽

Author(s):

Jovanka Ciric ◽

Gin Yee ◽

Carl Sechen

Keyword(s):

Technology Mapping ◽

Domino Logic ◽

Delay Minimization

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On nominal delay minimization in LUT-based FPGA technology mapping

Integration ◽

10.1016/0167-9260(94)90012-4 ◽

1994 ◽

Vol 18 (1) ◽

pp. 73-94 ◽

Cited By ~ 6

Author(s):

Jason Cong ◽

Yuzheng Ding

Keyword(s):

Technology Mapping ◽

Delay Minimization

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On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

Third International ACM Symposium on Field-Programmable Gate Arrays ◽

10.1109/fpga.1995.242045 ◽

1995 ◽

Cited By ~ 5

Author(s):

J. Cong ◽

Yuzheng Ding

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Integrating Technology: Mapping Digital Game Analogies to Science Instruction

Science Scope ◽

10.2505/4/ss18_041_07_88 ◽

2018 ◽

Vol 041 (07) ◽

Cited By ~ 1

Author(s):

Wendy Martin ◽

Marian Pasquale ◽

Megan Silander

Keyword(s):

Science Instruction ◽

Technology Mapping ◽

Digital Game ◽

Integrating Technology

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Educational technology - mapping the terrain with Bernstein as cartographer

Journal of Computer Assisted Learning ◽

10.1111/j.1365-2729.2010.00359.x ◽

2010 ◽

Vol 26 (6) ◽

pp. 523-534 ◽

Cited By ~ 15

Author(s):

L. Czerniewicz

Keyword(s):

Educational Technology ◽

Technology Mapping

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A game theoretic approach for delay minimization in slotted ALOHA

2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577) ◽

10.1109/icc.2004.1313302 ◽

2004 ◽

Cited By ~ 10

Author(s):

E. Altrnan ◽

D. Barman ◽

R. El Azouzi ◽

T. Jimenez

Keyword(s):

Theoretic Approach ◽

Slotted Aloha ◽

Delay Minimization ◽

Game Theoretic ◽

Game Theoretic Approach

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Application of Fast Mapping Techniques in Sudden Crisis

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.998-999.1553 ◽

2014 ◽

Vol 998-999 ◽

pp. 1553-1556

Author(s):

Hui Yuan

Keyword(s):

Economic Development ◽

Science And Technology ◽

Technology Mapping ◽

Fast Mapping ◽

Geological Disasters ◽

Great Progress ◽

Mapping Technology ◽

Mapping Techniques ◽

Crisis Situations

With the rapid economic development and the progress of science and technology, mapping technology has made great progress in our country. New mapping technologies are introduced and putted into use in more and more industry. In this paper, the fast mapping technologies are used to solve the sudden crisis situations, such as geological disasters and accidents.

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