Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537) ◽

10.1109/date.2000.840284 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Ciric ◽

G. Yee ◽

C. Sechen

Keyword(s):

Technology Mapping ◽

Domino Logic ◽

Delay Minimization

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Delay minimization and technology mapping of two-level structures and implementation using clock-delayed domino logic

Proceedings of the conference on Design, automation and test in Europe - DATE '00 ◽

10.1145/343647.343781 ◽

2000 ◽

Author(s):

Jovanka Ciric ◽

Gin Yee ◽

Carl Sechen

Keyword(s):

Technology Mapping ◽

Domino Logic ◽

Delay Minimization

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Combining technology mapping and placement for delay-minimization in FPGA designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.406709 ◽

1995 ◽

Vol 14 (9) ◽

pp. 1076-1084 ◽

Cited By ~ 1

Author(s):

Chau-Shen Chen ◽

Yu-Wen Tsay ◽

TingTing Hwang ◽

A.C.H. Wu ◽

Youn-Long Lin

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Technology mapping for domino logic

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1145/288548.288621 ◽

1998 ◽

Cited By ~ 15

Author(s):

Min Zhao ◽

Sachin S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic

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Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1109/dac.2001.935538 ◽

2002 ◽

Author(s):

S.K. Karandikar ◽

S.S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic

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On nominal delay minimization in LUT-based FPGA technology mapping

Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays - FPGA '95 ◽

10.1145/201310.201324 ◽

1995 ◽

Author(s):

Jason Cong ◽

Yuzheng Ding

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Technology mapping algorithms for domino logic

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/544536.544541 ◽

2002 ◽

Vol 7 (2) ◽

pp. 306-335 ◽

Cited By ~ 5

Author(s):

Min Zhao ◽

Sachin S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic ◽

Mapping Algorithms

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Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2003.817137 ◽

2003 ◽

Vol 11 (6) ◽

pp. 1094-1105 ◽

Cited By ~ 2

Author(s):

S.K. Karandikar ◽

S.S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic

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Technology mapping for domino logic

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287) ◽

10.1109/iccad.1998.742880 ◽

2002 ◽

Author(s):

Min Zhao ◽

S.S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic

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Simultaneous Technology Mapping and Placement for Delay Minimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2010.2089569 ◽

2011 ◽

Vol 30 (3) ◽

pp. 416-426 ◽

Cited By ~ 3

Author(s):

Yifang Liu ◽

Rupesh S. Shelar ◽

Jiang Hu

Keyword(s):

Technology Mapping ◽

Delay Minimization

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Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1145/378239.378527 ◽

2001 ◽

Cited By ~ 1

Author(s):

Srirang K. Karandikar ◽

S. Sapatnekar

Keyword(s):

Technology Mapping ◽

Domino Logic

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