Timing optimization by gate resizing and critical path identification

1993 ◽  
Author(s):  
Wen-Ben Jone ◽  
Chen-Liang Fang
Keyword(s):  
Critical Path ◽  
Timing Optimization ◽  
Gate Resizing ◽  
Critical Path Identification

scholarly journals Research of Intersection Groups Optimization Control Method Based on Critical Path Identification

2018 ◽  
Vol 173 ◽  
pp. 03068
Author(s):  
Ying Liu ◽  
Lv Fang ◽  
Jiayan Shen
Keyword(s):  
Control Algorithm ◽  
Control Method ◽  
Search Algorithm ◽  
Critical Path ◽  
Signal Timing ◽  
C Language ◽  
Phase Sequence ◽  
Traffic Operation ◽  
Intersection Control ◽  
Critical Path Identification

An optimal intersection groups control method based on critical path identification is proposed. The control algorithm uses a binary search to gradually determine the scope of the intersection groups, uses the duality method to express the intersection groups, uses breadth-first search algorithm to solve the critical path, and finally uses the branch-and-bound method to solve the lane canalization, realizes the optimized output of phase-sequence and timing of intersection control signals. The control algorithm is realized using C++ language, including the following functional modules: intersection range dynamic definition, critical path identification, space-time resource optimization, and online timing adjustment of signal timing parameters and so on. Finally, the control algorithm is verified by the actual road network of Changzhou City of China, the result shows that, the efficiency of traffic operation is significantly improved.

scholarly journals Timing-Driven-Testable Convergent Tree Adders

VLSI Design ◽  
2002 ◽  
Vol 15 (3) ◽  
pp. 637-645
Author(s):  
Johnnie A. Huang ◽  
Chien-In Henry Chen
Keyword(s):  
Critical Path ◽  
Regular Structure ◽  
Tree Structure ◽  
Vlsi Implementation ◽  
Timing Optimization ◽  
Complex Arithmetic ◽  
Area Overhead ◽  
Arithmetic Units

Carry lookahead adders have been, over the years, implemented in complex arithmetic units due to their regular structure which leads to efficient VLSI implementation for fast adders. In this paper, timing-driven testability synthesis is first performed on a tree adder. It is shown that the structure of the tree adder provides for a high fanout with an imbalanced tree structure, which likely contributes to a racing effect and increases the delay of the circuit. The timing optimization is then realized by reducing the maximum fanout of the adder and by balancing the tree circuit. For a 56-b testable tree adder, the optimization produces a 6.37%increase in speed of the critical path while only contributing a 2.16% area overhead. The full testability of the circuit is achieved in the optimized adder design.

Critical path identification in the context of a workflow

2002 ◽  
Vol 44 (7) ◽  
pp. 405-417 ◽  
Author(s):  
Duk-Ho Chang ◽  
Jin Hyun Son ◽  
Myoung Ho Kim
Keyword(s):  
Critical Path ◽  
Critical Path Identification

scholarly journals Critical Path Identification and Load Balancing Strategy for Concurrent Projects

2001 ◽  
Vol 121 (6) ◽  
pp. 695-704 ◽  
Author(s):  
Hiroaki Sugihara ◽  
Yasutaka Fujimoto ◽  
John Takuya Ootsuki ◽  
Takashi Sekiguchi
Keyword(s):  
Load Balancing ◽  
Critical Path ◽  
Critical Path Identification
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