Probabilistic Critical Path Identification for Cost-Effective Monitoring of Service-Based Systems

2012 ◽  
Author(s):  
Qiang He ◽  
Jun Han ◽  
Yun Yang ◽  
Jean-Guy Schneider ◽  
Hai Jin ◽  
...  
Keyword(s):  
Critical Path ◽  
Cost Effective ◽  
Critical Path Identification

scholarly journals Power and Area Efficient Clock Stretching and Critical Path Reshaping for Error Resilience

2019 ◽  
Vol 9 (1) ◽  
pp. 5
Author(s):  
Mini Jayakrishnan ◽  
Alan Chang ◽  
Tony Tae-Hyoung Kim
Keyword(s):  
Critical Path ◽  
Error Resilience ◽  
Cost Effective ◽  
Advanced Technology ◽  
Worst Case ◽  
Flip Flop ◽  
Smart Products ◽  
Run Time ◽  
Critical Paths ◽  
And Performance

Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively.

scholarly journals Research of Intersection Groups Optimization Control Method Based on Critical Path Identification

2018 ◽  
Vol 173 ◽  
pp. 03068
Author(s):  
Ying Liu ◽  
Lv Fang ◽  
Jiayan Shen
Keyword(s):  
Control Algorithm ◽  
Control Method ◽  
Search Algorithm ◽  
Critical Path ◽  
Signal Timing ◽  
C Language ◽  
Phase Sequence ◽  
Traffic Operation ◽  
Intersection Control ◽  
Critical Path Identification

An optimal intersection groups control method based on critical path identification is proposed. The control algorithm uses a binary search to gradually determine the scope of the intersection groups, uses the duality method to express the intersection groups, uses breadth-first search algorithm to solve the critical path, and finally uses the branch-and-bound method to solve the lane canalization, realizes the optimized output of phase-sequence and timing of intersection control signals. The control algorithm is realized using C++ language, including the following functional modules: intersection range dynamic definition, critical path identification, space-time resource optimization, and online timing adjustment of signal timing parameters and so on. Finally, the control algorithm is verified by the actual road network of Changzhou City of China, the result shows that, the efficiency of traffic operation is significantly improved.

scholarly journals Dynamic Fault-Tolerant Workflow Scheduling with Hybrid Spatial-Temporal Re-Execution in Clouds

Information ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 169 ◽  
Author(s):  
Na Wu ◽  
Decheng Zuo ◽  
Zhan Zhang
Keyword(s):  
Large Scale ◽  
Fault Tolerant ◽  
Critical Path ◽  
High Reliability ◽  
Low Cost ◽  
Cost Effective ◽  
Scientific Workflow ◽  
Workflow Scheduling ◽  
Workflow Execution ◽  
Computing Environments

Improving reliability is one of the major concerns of scientific workflow scheduling in clouds. The ever-growing computational complexity and data size of workflows present challenges to fault-tolerant workflow scheduling. Therefore, it is essential to design a cost-effective fault-tolerant scheduling approach for large-scale workflows. In this paper, we propose a dynamic fault-tolerant workflow scheduling (DFTWS) approach with hybrid spatial and temporal re-execution schemes. First, DFTWS calculates the time attributes of tasks and identifies the critical path of workflow in advance. Then, DFTWS assigns appropriate virtual machine (VM) for each task according to the task urgency and budget quota in the phase of initial resource allocation. Finally, DFTWS performs online scheduling, which makes real-time fault-tolerant decisions based on failure type and task criticality throughout workflow execution. The proposed algorithm is evaluated on real-world workflows. Furthermore, the factors that affect the performance of DFTWS are analyzed. The experimental results demonstrate that DFTWS achieves a trade-off between high reliability and low cost objectives in cloud computing environments.

scholarly journals Cost Effective Implementation of Fixed Point Adders for LUT based FPGAs using Technology Dependent Optimizations

2015 ◽  
Vol 19 (1) ◽  
pp. 14 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz
Keyword(s):  
Fixed Point ◽  
Critical Path ◽  
Minimum Cost ◽  
Cost Effective ◽  
Path Delay ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Volume Production ◽  
On Chip ◽  
The Cost

Modern day field programmable gate arrays(FPGAs) have very huge and versatile logic resources resulting inthe migration of their application domain from prototypedesigning to low and medium volume production designing.Unfortunately most of the work pertaining to FPGAimplementations does not focus on the technology dependentoptimizations that can implement a desired functionality withreduced cost. In this paper we consider the mapping of simpleripple carry fixed-point adders (RCA) on look-up table (LUT)based FPGAs. The objective is to transform the given RCABoolean network into an optimized circuit netlist that canimplement the desired functionality with minimum cost. Weparticularly focus on 6-input LUTs that are inherent in all themodern day FPGAs. Technology dependent optimizations arecarried out to utilize this FPGA primitive efficiently and theresult is compared against various adder designs. Theimplementation targets the XC5VLX30-3FF324 device fromXilinx Virtex-5 FPGA family. The cost of the circuit is expressedin terms of the resources utilized, critical path delay and theamount of on-chip power dissipated. Our implementation resultsshow a reduction in resources usage by at least 50%; increase inspeed by at least 10% and reduction in dynamic powerdissipation by at least 30%. All this is achieved without anytechnology independent (architectural) modification.

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