Computer architecture and instruction set design

1973 ◽  
Author(s):  
P. C. Anagnostopoulos ◽  
M. J. Michel ◽  
G. H. Sockut ◽  
G. M. Stabler ◽  
A. van Dam
Keyword(s):  
Computer Architecture ◽  
Set Design ◽  
Instruction Set

scholarly journals Beyond imitation: Zero-shot task transfer on robots by learning concepts as cognitive programs

2019 ◽  
Vol 4 (26) ◽  
pp. eaav3150 ◽  
Author(s):  
Miguel Lázaro-Gredilla ◽  
Dianhuan Lin ◽  
J. Swaroop Guntupalli ◽  
Dileep George
Keyword(s):  
Working Memory ◽  
Computer Architecture ◽  
Arm Movement ◽  
Physical World ◽  
Instruction Set ◽  
Computational Framework ◽  
Perception System ◽  
Image Pairs ◽  
High Level ◽  
Transfer Tasks

Humans can infer concepts from image pairs and apply those in the physical world in a completely different setting, enabling tasks like IKEA assembly from diagrams. If robots could represent and infer high-level concepts, then it would notably improve their ability to understand our intent and to transfer tasks between different environments. To that end, we introduce a computational framework that replicates aspects of human concept learning. Concepts are represented as programs on a computer architecture consisting of a visual perception system, working memory, and action controller. The instruction set of this cognitive computer has commands for parsing a visual scene, directing gaze and attention, imagining new objects, manipulating the contents of a visual working memory, and controlling arm movement. Inferring a concept corresponds to inducing a program that can transform the input to the output. Some concepts require the use of imagination and recursion. Previously learned concepts simplify the learning of subsequent, more elaborate concepts and create a hierarchy of abstractions. We demonstrate how a robot can use these abstractions to interpret novel concepts presented to it as schematic images and then apply those concepts in very different situations. By bringing cognitive science ideas on mental imagery, perceptual symbols, embodied cognition, and deictic mechanisms into the realm of machine learning, our work brings us closer to the goal of building robots that have interpretable representations and common sense.

scholarly journals A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

2013 ◽  
Vol 2013 ◽  
pp. 1-26 ◽  
Author(s):  
Jia Hao Kong ◽  
Li-Minn Ang ◽  
Kah Phooi Seng
Keyword(s):  
Computer Architecture ◽  
Nonlinear Property ◽  
Set Partitioning ◽  
Advanced Encryption Standard ◽  
Instruction Set ◽  
Selective Encryption ◽  
Low Area ◽  
Gate Count ◽  
Hierarchical Trees ◽  
Spiht Algorithm

The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.

PPSim: A Cycle-Accurate Simulator for PowerPC Instruction Set

2013 ◽  
Vol 325-326 ◽  
pp. 1766-1769
Author(s):  
Xiao Peng Gao ◽  
Ping Yang Guo
Keyword(s):  
Computer Architecture ◽  
Branch Prediction ◽  
Instruction Set ◽  
Order Scheduling ◽  
Unit Management ◽  
Function Unit ◽  
And Function

Simulators play an important part in computer architecture research. As for specific microarchitecture study, which focuses on the accurate behavior of out-of-order scheduling, ALU contention, and function unit management, an over-simplified abstraction is not sufficient to represent modern processor organizations. Thus cycle-accurate simulators are introduced to describe the accurate behavior in target microarchitecture. In cycle-accurate simulators, the timing feature within function units is simulated. This paper presents PPSim, a cycle-accurate PowerPC instruction set simulator, which models the cache, branch prediction, and out of order pipeline in PowerPC microarchitecture.

scholarly journals A Compression Instruction Set Design based on RISC-V for Network Packet Forwarding

2018 ◽  
Vol 1026 ◽  
pp. 012001
Author(s):  
Z Cao ◽  
Q Lv ◽  
Y Wang ◽  
M Wen ◽  
N Wu ◽  
...  
Keyword(s):  
Set Design ◽  
Packet Forwarding ◽  
Instruction Set

scholarly journals DESIGN OF FIR FILTER ALGORITHM FOR NOISE REMOVAL IN ECG SIGNAL USING OPEN CORE SoC

2021 ◽  
Vol 10 (2) ◽  
pp. , 1044-1046
Keyword(s):  
Computer Architecture ◽  
Noise Removal ◽  
Fir Filter ◽  
Ecg Signal ◽  
Instruction Set ◽  
Cycle Count ◽  
The Many ◽  
Processor Cores ◽  
Open Core ◽  
Dsp Applications

The emerging technology in computer architecture has led to the development of various ISAs depending on the needs of the desired technology, architectures, and processor cores. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, RISC-V, etc. This has provided the path to implement various functions on an open core SoC Platform. Among the many DSP applications, the FIR filter has been implemented on an open core SoC platform that uses RISCV. Here specifically filtering of noise from ECG signal. The performance cycle count has been obtained for the same and compared with its counterpart ARM M7 on the Keil platform.

Sign in / Sign up

Export Citation Format

Share Document