Reduced instruction set computer architecture

1988 ◽  
Vol 76 (1) ◽  
pp. 38-55 ◽  
Author(s):  
W. Stallings
Keyword(s):  
Computer Architecture ◽  
Instruction Set ◽  
Reduced Instruction Set Computer

scholarly journals An Accurate and Efficient Timing Prediction Framework for Wide Supply Voltage Design Based on Learning Method

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 580
Author(s):  
Peng Cao ◽  
Wei Bao ◽  
Jingjing Guo
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Instruction Set ◽  
Timing Verification ◽  
Static Timing Analysis ◽  
Static Timing ◽  
Threshold Voltages ◽  
Layer Stacking ◽  
Reduced Instruction Set Computer

The wide voltage design methodology has been widely employed in the state-of-the-art circuit design with the advantage of remarkable power reduction and energy efficiency enhancement. However, the timing verification issue for multiple PVT (process–voltage–temperature) corners rises due to unacceptable analysis effort increase for multiple supply voltage nodes. Moreover, the foundry-provided timing libraries in the traditional STA (static timing analysis) approach are only available for the nominal supply voltage with limited voltage scaling, which cannot support timing verification for low voltages down to near- or sub-threshold voltages. In this paper, a learning-based approach for wide voltage design is proposed where feature engineering is performed to enhance the correlation among PVT corners based on a dilated CNN (convolutional neural network) model, and an ensemble model is utilized with two-layer stacking to improve timing prediction accuracy. The proposed method was verified with a commercial RISC (reduced instruction set computer) core under the supply voltage nodes ranging from 0.5 V to 0.9 V. Experimental results demonstrate that the prediction error is limited by 4.9% and 7.9%, respectively, within and across process corners for various working temperatures, which achieves up to 4.4× and 3.9× precision enhancement compared with related learning-based methods.

scholarly journals An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

Symmetry ◽  
2019 ◽  
Vol 11 (7) ◽  
pp. 938
Author(s):  
Syed Rameez Naqvi ◽  
Ali Roman ◽  
Tallha Akram ◽  
Majed M. Alhaisoni ◽  
Muhammad Naeem ◽  
...  
Keyword(s):  
Assembly Language ◽  
Optimization Method ◽  
Instruction Set ◽  
Mathematical Performance ◽  
Optimization Framework ◽  
And Performance ◽  
Reduced Instruction Set Computer ◽  
High Level ◽  
The Given ◽  
Primary Contribution

Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

scholarly journals Beyond imitation: Zero-shot task transfer on robots by learning concepts as cognitive programs

2019 ◽  
Vol 4 (26) ◽  
pp. eaav3150 ◽  
Author(s):  
Miguel Lázaro-Gredilla ◽  
Dianhuan Lin ◽  
J. Swaroop Guntupalli ◽  
Dileep George
Keyword(s):  
Working Memory ◽  
Computer Architecture ◽  
Arm Movement ◽  
Physical World ◽  
Instruction Set ◽  
Computational Framework ◽  
Perception System ◽  
Image Pairs ◽  
High Level ◽  
Transfer Tasks

Humans can infer concepts from image pairs and apply those in the physical world in a completely different setting, enabling tasks like IKEA assembly from diagrams. If robots could represent and infer high-level concepts, then it would notably improve their ability to understand our intent and to transfer tasks between different environments. To that end, we introduce a computational framework that replicates aspects of human concept learning. Concepts are represented as programs on a computer architecture consisting of a visual perception system, working memory, and action controller. The instruction set of this cognitive computer has commands for parsing a visual scene, directing gaze and attention, imagining new objects, manipulating the contents of a visual working memory, and controlling arm movement. Inferring a concept corresponds to inducing a program that can transform the input to the output. Some concepts require the use of imagination and recursion. Previously learned concepts simplify the learning of subsequent, more elaborate concepts and create a hierarchy of abstractions. We demonstrate how a robot can use these abstractions to interpret novel concepts presented to it as schematic images and then apply those concepts in very different situations. By bringing cognitive science ideas on mental imagery, perceptual symbols, embodied cognition, and deictic mechanisms into the realm of machine learning, our work brings us closer to the goal of building robots that have interpretable representations and common sense.

scholarly journals A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box

2013 ◽  
Vol 2013 ◽  
pp. 1-26 ◽  
Author(s):  
Jia Hao Kong ◽  
Li-Minn Ang ◽  
Kah Phooi Seng
Keyword(s):  
Computer Architecture ◽  
Nonlinear Property ◽  
Set Partitioning ◽  
Advanced Encryption Standard ◽  
Instruction Set ◽  
Selective Encryption ◽  
Low Area ◽  
Gate Count ◽  
Hierarchical Trees ◽  
Spiht Algorithm

The “S-box” algorithm is a key component in the Advanced Encryption Standard (AES) due to its nonlinear property. Various implementation approaches have been researched and discussed meeting stringent application goals (such as low power, high throughput, low area), but the ultimate goal for many researchers is to find a compact and small hardware footprint for the S-box circuit. In this paper, we present our version of minimized S-box with two separate proposals and improvements in the overall gate count. The compact S-box is adopted with a compact and optimum processor architecture specifically tailored for the AES, namely, the compact instruction set architecture (CISA). To further justify and strengthen the purpose of the compact crypto-processor’s application, we have also presented a selective encryption architecture (SEA) which incorporates the CISA as a part of the encryption core, accompanied by the set partitioning in hierarchical trees (SPIHT) algorithm as a complete selective encryption system.

PPSim: A Cycle-Accurate Simulator for PowerPC Instruction Set

2013 ◽  
Vol 325-326 ◽  
pp. 1766-1769
Author(s):  
Xiao Peng Gao ◽  
Ping Yang Guo
Keyword(s):  
Computer Architecture ◽  
Branch Prediction ◽  
Instruction Set ◽  
Order Scheduling ◽  
Unit Management ◽  
Function Unit ◽  
And Function

Simulators play an important part in computer architecture research. As for specific microarchitecture study, which focuses on the accurate behavior of out-of-order scheduling, ALU contention, and function unit management, an over-simplified abstraction is not sufficient to represent modern processor organizations. Thus cycle-accurate simulators are introduced to describe the accurate behavior in target microarchitecture. In cycle-accurate simulators, the timing feature within function units is simulated. This paper presents PPSim, a cycle-accurate PowerPC instruction set simulator, which models the cache, branch prediction, and out of order pipeline in PowerPC microarchitecture.

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