A new large-scale integrated metallization-failure mechanism

1985 ◽  
Vol 63 (6) ◽  
pp. 901-905
Author(s):  
S. P. Bellier ◽  
R. F. Haythornthwaite
Keyword(s):  
Integrated Circuits ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Large Scale ◽  
Silicon Oxide ◽  
High Reliability ◽  
Water System ◽  
Ultrasonic Agitation ◽  
Scanning Auger Microprobe ◽  
Aluminum Metallization

A new integrated-circuit metallization-failure mechanism is reported. The aluminum metallization sometimes disintegrates during ultrasonic agitation despite the fact that the aluminium–silicon oxide–water system is thermodynamically stable under conditions normally encountered by integrated circuits. The disintegration reduces conductor cross section and increases the probability of failure by electromigration. Faulty batches of metallization from six manufacturers have been found; one batch of devices, which failed abnormally early through electromigration, had the faulty metallization.Scanning–electron–microscope examination revealed that foreign material or voids were sometimes visible between the aluminum grains but there was often no visible indication of the problem areas. Scanning Auger microprobe examination revealed nitrogen and oxygen in the aluminum of faulty batches, and carbon was also present in the areas that lifted. Aluminum, which was unaffected by ultrasonic agitation, had no additional elements.Experiments in controlling the evaporation environment to increase the probability of incorporating oxygen, nitrogen, and carbon into the aluminum layer were unsuccessful.Ultrasonic agitation provides an economic possibility for screening devices with unstable metallization. It can be introduced during wafer manufacture or as a sampling screen on completed devices for high reliability applications.

In SEM a New Method of Internal Micrographic Visualization of Semiconductor Materials and IC by Crossing the Surface

2001 ◽  
Vol 7 (S2) ◽  
pp. 484-485
Author(s):  
Ling Xiao ◽  
Zhuguan Liang ◽  
Yawen Li ◽  
Jian Wang ◽  
Kailin Zhou ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Silicon Oxide ◽  
Detection Method ◽  
New Method ◽  
Semiconductor Materials ◽  
Contactless Method ◽  
Quality And Reliability ◽  
Nitride Layers ◽  
Scanning Electron

In the paper, we firstly publish a new method of internal micrographic visualization of semiconductor and IC. The quality and reliability of the semiconductor materials (SM) and the integrated circuits (IC) have always been concerned Having a high resolution, high reliable and nondestructive detection method is the key element for their improvements.Silicon oxide layers are used to provide the electrical insulation in the multi-structured ICs. The IC device surfaces are often protected by silicon oxide and silicon nitride layers. Therefore, these insulation layers also cover any inhomogeneity and defect located within the IC devices. It is necessary to have an examining method to detect those defects that are under the insulation layers without damaging the samples. However, the conventional scanning electron microscope (SEM) cannot be utilized to image and examine the surfaces that are positioned below the insulation layers.Novel nondestructive and contactless method has been developed in our laboratory to obtain the internal micrograph that crosses the surface of the semiconductor material and the integrated circuit.

scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

A Comprehensive Test Compression Scheme Based on Precomputed Test Sets

2013 ◽  
Vol 756-759 ◽  
pp. 533-541
Author(s):  
Zhi Jian Tian ◽  
Fa Yong Zhao
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Test Pattern ◽  
Compression Scheme ◽  
Run Length ◽  
Rearrangement Algorithm ◽  
Long Run ◽  
Assignment Strategy ◽  
Run Lengths

To cope with increasingly rigorous challenges that large scale digital integrated circuit testing is confronted with, a comprehensive compression scheme consisting of test-bit rearrangement algorithm, run-length assignment strategy and symmetrical code is proposed. The presented test-bit rearrangement algorithm can fasten dont-care bits, 0s or 1s in every test pattern on one of its end to the greatest extent so as to lengthen end-run blocks and decrease number of short run-lengths. A dynamical dont-care assignment strategy based on run-lengths can be used to specify the remaining dont-care bits after the test-bit rearrangement, which can decrease run-length splitting and maximize length of run-lengths. The symmetrical code benefits from long run-lengths and only uses 2 4-bit short code words to identify end-run blocks almost as long as a test pattern, and hence the utilization ratio of code words can be heightened. The presented experiment results show that the proposed comprehensive scheme can obtain very higher data compression ratios than other compression ones published up to now, especially for large scale digital integrated circuits, and considerably decrease test power dissipations.

scholarly journals Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

2019 ◽  
Vol 9 (20) ◽  
pp. 4212 ◽  
Author(s):  
Mingqiang Huang ◽  
Xingli Wang ◽  
Guangchao Zhao ◽  
Philippe Coquet ◽  
Bengkang Tay
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
2D Materials ◽  
Two Dimensional ◽  
Ternary Logic ◽  
Chip Area ◽  
Logic Devices ◽  
Ripple Carry Adder ◽  
Data Density

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

scholarly journals Free Space Intra-Datacenter Interconnects Based on 2D Optical Beam Steering Enabled by Photonic Integrated Circuits

Photonics ◽  
2018 ◽  
Vol 5 (3) ◽  
pp. 21 ◽  
Author(s):  
Charidimos Chaintoutis ◽  
Behnam Shariati ◽  
Adonis Bogris ◽  
Paul Dijk ◽  
Chris Roeloffzen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Data Center ◽  
Free Space ◽  
Large Scale ◽  
Beam Steering ◽  
Optical Beam ◽  
Switching Network ◽  
Free Space Optical ◽  
Data Center Networks

Data centers are continuously growing in scale and can contain more than one million servers spreading across thousands of racks; requiring a large-scale switching network to provide broadband and reconfigurable interconnections of low latency. Traditional data center network architectures, through the use of electrical packet switches in a multi-tier topology, has fundamental weaknesses such as oversubscription and cabling complexity. Wireless intra-data center interconnection solutions have been proposed to deal with the cabling problem and can simultaneously address the over-provisioning problem by offering efficient topology re-configurability. In this work we introduce a novel free space optical interconnect solution for intra-data center networks that utilizes 2D optical beam steering for the transmitter, and high bandwidth wide-area photodiode arrays for the receiver. This new breed of free space optical interconnects can be developed on a photonic integrated circuit; offering ns switching at sub-μW consumption. The proposed interconnects together with a networking architecture that is suitable for utilizing those devices could support next generation intra-data center networks, fulfilling the requirements of seamless operation, high connectivity, and agility in terms of the reconfiguration time.

Stress Measurements in Thin Films Deposited on Single Crystal Substrates Through X-ray Topography Techniques

1976 ◽  
Vol 20 ◽  
pp. 273-281 ◽  
Author(s):  
E. W. Hearn
Keyword(s):  
Thin Films ◽  
Single Crystal ◽  
Integrated Circuit ◽  
Large Scale ◽  
Silicon Oxide ◽  
Double Crystal ◽  
X Ray ◽  
Quantitative Measurements ◽  
Order Of Magnitude ◽  
Polycrystalline Silicon Films

The application of x-ray topographic techniques to the measurement of stress in thin, films is discussed. Quantitative measurements of stresses in thin films deposited on semiconductor substrates, such as silicon, are also discussed. Double crystal and single crystal techniques are used for such measurements. Both techniques are applied to the measurements of stress in silicon oxide, silicon nitride and polycrystalline silicon films on silicon. The doubly crystal technique is useful for measurements of stresses as low as 109 dynes/cm2 in films only 1000A thick. The single crystal technique is less sensitive by one order of magnitude. The advantage of the single crystal technique is its simplicity and speed. It is useful for large scale measurements as encountered in the manufacture of silicon integrated circuit.

The Challenge of GaAs Heterojunction Bipolar Transistor Integrated Circuit Technology.

1988 ◽  
Vol 144 ◽  
Author(s):  
Han-Tzong Yuan
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
The Status ◽  
Impurity Doping

ABSTRACTThe status and progress of AlGaAs/GaAs heterojunction bipolar transistor integrated circuits are reviewed. The challenge of fabricating large-scale integrated circuits using heterojunction bipolar transistors is discussed. Specifically, the issues related to low defect epitaxial materials, localized impurity doping techniques, simple and reliable ohmic contacts, and multilevel interconnects are examined.

Preparation of Hexaphenylamine Cyclotriphosphazene and its Green Flame Retardance on Epoxy Molding Compound for Large-Scale Integrated Circuit Packaging

2011 ◽  
Vol 239-242 ◽  
pp. 1386-1390
Author(s):  
Ming Shan Yang ◽  
Lin Kai Li
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Flame Retardants ◽  
Large Scale ◽  
Reaction Rate ◽  
Flame Retardance ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Synthesis Parameters ◽  
Halogen Free

The hexaphenylamine cyclotriphosphazene (HPACTPZ) was synthesized using titrating technology of hexachlorocyclotriphosphazene solution and the synthesis parameters were investigated, and the structure of HPACTPZ was analyzed by FTIR and NMR in this paper. Using HPACTPZ synthesized in the work as flame retardant, the epoxy molding compound(EMC) for packaging of large-scale integrated circuits with halogen-free flame retardance was prepared. The results have shown that the flame retardance of EMC flame-retardanced by HPACTPZ was up to UL 94 V0 rating(3.2mm) and the oxygen index of the EMC was up to 35.8%, which indicates that HPACTPZ has much better flame retardance for EMC than traditional halogen flame-retardants. Meanwhile, HPACTPZ accelerated the curing reaction rate of EMC, which can be used for manufacturing the quick-curing EMCs or afterward-curing-free EMCs.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

Study of Pore Architecture in Silicon Oxide Thin Films by Variable-energy Positron Annihilation Spectroscopy

2002 ◽  
Vol 751 ◽  
Author(s):  
Kenji Ito ◽  
Yoshinori Kobayashi ◽  
Runsheng Yu ◽  
Kouichi Hirata ◽  
Hisashi Togashi ◽  
...  
Keyword(s):  
Thin Films ◽  
Porous Silicon ◽  
Integrated Circuits ◽  
Positron Annihilation ◽  
Large Scale ◽  
Silicon Oxide ◽  
Positron Annihilation Spectroscopy ◽  
Oxide Thin Films ◽  
Intensive Investigation ◽  
Variable Energy

ABSTRACTApplication of porous silicon oxide thin films to nanotechnology is under intensive investigation. Introducing a large amount of nano pores into a silicon oxide matrix is important to develop low-k dielectrics for future ultra-large-scale integrated circuits (ULSI). In this work, we applied variable-energy positron annihilation to the characterization of porous silicon oxide thin films fabricated on silicon wafers by sputtering and spincoating. It was found that the sputtered film has higher open pore connectivity than that of the spincoated low-k film.

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