scholarly journals Quasi-ballistic carbon nanotube array transistors with current density exceeding Si and GaAs

2016 ◽  
Vol 2 (9) ◽  
pp. e1601240 ◽  
Author(s):  
Gerald J. Brady ◽  
Austin J. Way ◽  
Nathaniel S. Safron ◽  
Harold T. Evensen ◽  
Padma Gopalan ◽  
...  
Keyword(s):  
Current Density ◽  
High Speed ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Oxide Thickness ◽  
Semiconductor Electronics ◽  
Conductance Limit ◽  
Previous State ◽  
Parallel Arrays ◽  
Array Performance

Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e2/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm−1, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm−1, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm−1 and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.

scholarly journals High-speed black phosphorus field-effect transistors approaching ballistic limit

2019 ◽  
Vol 5 (6) ◽  
pp. eaau3194 ◽  
Author(s):  
Xuefei Li ◽  
Zhuoqing Yu ◽  
Xiong Xiong ◽  
Tiaoyang Li ◽  
Tingting Gao ◽  
...  
Keyword(s):  
High Speed ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Black Phosphorus ◽  
Saturation Velocity ◽  
High Drive ◽  
High Carrier Mobility ◽  
High Carrier ◽  
Strong Candidate

As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/μm at 300 K and 1.6 mA/μm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Nanoscale transistors

2017 ◽  
Author(s):  
Sandip Tiwari
Keyword(s):  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Dimensional Change ◽  
Real Space ◽  
Operational Characteristics ◽  
Statistical Variations ◽  
Channel Transport ◽  
And Control ◽  
Long Channel ◽  
Detailed Nature

This chapter brings together the physical underpinnings of field-effect transistors operating in their nanoscale limits. It tackles the change in dominant behavior from scattering-limited long-channel transport to mesoscopic and few scattering events limits in quantized channels. It looks at electrostatics and a transistor’s controllability as dimensions are shrunk—the interplay of geometry and control—and then brings out the operational characteristics in “off”-state, e.g., the detailed nature of insulator’s implications or threshold voltage’s statistical variations grounded in short-range and long-range effects, and “on”-state, where quantization, quantized channels, ballistic transport and limited scattering are important. It also explores the physical behavior for zero bandgap and monoatomic layer materials by focusing on real-space and reciprocal-space funneling as one of the important dimensional change consequences through a discussion of parasitic resistances.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

scholarly journals Comparative Study ofSiO2,Al2O3, and BeO Ultrathin Interfacial Barrier Layers in Si Metal-Oxide-Semiconductor Devices

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
J. H. Yum ◽  
J. Oh ◽  
Todd. W. Hudnall ◽  
C. W. Bielawski ◽  
G. Bersuker ◽  
...  
Keyword(s):  
Metal Oxide ◽  
High Performance ◽  
Field Effect Transistors ◽  
Beryllium Oxide ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Flat Band ◽  
Effective Electron

In a previous study, we have demonstrated that beryllium oxide (BeO) film grown by atomic layer deposition (ALD) on Si and III-V MOS devices has excellent electrical and physical characteristics. In this paper, we compare the electrical characteristics of inserting an ultrathin interfacial barrier layer such as SiO2, Al2O3, or BeO between the HfO2gate dielectric and Si substrate in metal oxide semiconductor capacitors (MOSCAPs) and n-channel inversion type metal oxide semiconductor field effect transistors (MOSFETs). Si MOSCAPs and MOSFETs with a BeO/HfO2gate stack exhibited high performance and reliability characteristics, including a 34% improvement in drive current, slightly better reduction in subthreshold swing, 42% increase in effective electron mobility at an electric field of 1 MV/cm, slightly low equivalent oxide thickness, less stress-induced flat-band voltage shift, less stress induced leakage current, and less interface charge.

AlGaN/GaN HEMTs: RECENT DEVELOPMENTS AND FUTURE DIRECTIONS

2008 ◽  
Vol 18 (04) ◽  
pp. 913-922 ◽  
Author(s):  
SIDDHARTH RAJAN ◽  
UMESH K. MISHRA ◽  
TOMÁS PALACIOS
Keyword(s):  
Field Effect ◽  
High Speed ◽  
Digital Circuits ◽  
Field Effect Transistors ◽  
Rf Power ◽  
Power Performance ◽  
Future Directions ◽  
Recent Developments ◽  
Gan Hemts ◽  
State Of Art

This paper provides an overview of recent work and future directions in Gallium Nitride transistor research. We discuss the present status of Ga -polar AlGaN / GaN HEMTs and the innovations that have led to record RF power performance. We describe the development of N -polar AlGaN / GaN HEMTs with microwave power performance comparable with state-of-art Ga -polar AlGaN / GaN HEMTs. Finally we will discuss how GaN -based field effect transistors could be promising for a less obvious application: low-power high-speed digital circuits.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

Estimation of Time Variation of Current Density in a 50 kA Lightning Impulse Arc using High Speed Cameras

2021 ◽  
Author(s):  
Tomoyuki Nakano ◽  
Masashi Kotari ◽  
Toshiya Ohtaka ◽  
Yutaka Goda ◽  
Mikimasa Iwata
Keyword(s):  
Current Density ◽  
Time Variation ◽  
High Speed ◽  
Lightning Impulse ◽  
Estimation Of Time

scholarly journals High drain-current-density and high breakdown-field Al0.36Ga0.64N-channel heterojunction filed-effect transistors with a dual AlN/AlGaInN barrier layer

2022 ◽  
Author(s):  
Akiyoshi Inoue ◽  
Sakura Tanaka ◽  
Takashi Egawa ◽  
Makoto Miyoshi
Keyword(s):  
Current Density ◽  
Barrier Layer ◽  
Ohmic Contacts ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Device Fabrication ◽  
Breakdown Field ◽  
Field Plate ◽  
Order Of Magnitude ◽  
State Breakdown

Abstract In this study, we fabricated and characterized heterojunction field-effect transistors (HFETs) based on an Al0.36Ga0.64N-channel heterostructure with a dual AlN/AlGaInN barrier layer. The device fabrication was accomplished by adopting a regrown n++-GaN layer for ohmic contacts. The fabricated HFETs with a gate length of 2 μm and a gate-to-drain distance of 6 μm exhibited an on-state drain current density as high as approximately 270 mA/mm and an off-state breakdown voltage of approximately 1 kV, which corresponds to an off-state critical electric field of 166 V/μm. This breakdown field, as a comparison in devices without field-plate electrodes, reaches approximately four-fold higher than that for conventional GaN-channel HFETs and was considered quite reasonable as an Al0.36Ga0.64N-channel transistor. It was also confirmed that the devices adopting the dual AlN/AlGaInN barrier layer showed approximately one order of magnitude smaller gate leakage currents than those for devices without the top AlN barrier layer.

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