1.4 Gbit/S Optical DPSK Heterodyne Transmission System Experiment

1989 ◽  
Author(s):  
J-M. P. Delavaux ◽  
L. D. Tzeng ◽  
M. Dixon
1983 ◽  
Vol 19 (13) ◽  
pp. 458 ◽  
Author(s):  
R.J.S. Bates ◽  
J.D. Spalink ◽  
S.J. Butterfield ◽  
J. Lipson ◽  
C.A. Burrus ◽  
...  

1983 ◽  
Author(s):  
J.-D. Spalink ◽  
R. J. S. Bates ◽  
S. J. Butterfield ◽  
J. Lipson ◽  
C. A. Burrus ◽  
...  

1992 ◽  
Vol 28 (16) ◽  
pp. 1484 ◽  
Author(s):  
T. Imai ◽  
M. Murakami ◽  
Y. Fukada ◽  
M. Aiki ◽  
T. Ito

1987 ◽  
Vol 23 (19) ◽  
pp. 1030 ◽  
Author(s):  
R. Heidemann ◽  
U. Scholz ◽  
B. Wedding

1988 ◽  
Vol 24 (21) ◽  
pp. 1335 ◽  
Author(s):  
J.M.P. Delavaux ◽  
R.W. Smith ◽  
L.D. Tzeng ◽  
J.R. Simpson ◽  
A.J. Ritger ◽  
...  

1992 ◽  
Vol 28 (19) ◽  
pp. 1852
Author(s):  
T. Imai ◽  
M. Murakami ◽  
Y. Fukada ◽  
M. Aiki ◽  
T. Ito

2013 ◽  
Vol 401-403 ◽  
pp. 1918-1922
Author(s):  
Xiao Hong Wang ◽  
Xiao Yu Zhang ◽  
Li Wu ◽  
Shu Sheng Peng

In this paper, a new 1-wire transmission system for the host-slave communication is introduced, which is composed of STM32 embedded host system, CPLD logic control system and PIC slave system. The transmission line is not only for data transmission between host and 32-way slave, but also for power supply for 32-way slave. This paper details the hardware and software implementation method of each component module based on the given system function, and highlights the circuit design method of power and signal transmission on the same line in the 1-wire transmission system. Experiment results are shown in the final chapter.


Sign in / Sign up

Export Citation Format

Share Document