Integrated Optics On Silicon Substrate : A Way To Achieve Complex Optical Circuits

1986 ◽  
Author(s):  
S. Valette ◽  
P. Mottier ◽  
J. Lizet ◽  
P. Gidon ◽  
J. P. Jadot ◽  
...  
Keyword(s):  
Integrated Optics ◽  
Silicon Substrate ◽  
Optical Circuits

Active Silicon Integrated Optical Circuits

1997 ◽  
Vol 486 ◽  
Author(s):  
Tim D. Bestwick
Keyword(s):  
Integrated Optics ◽  
Single Mode ◽  
Major Product ◽  
Silicon On Insulator ◽  
Integrated Optics Devices ◽  
Silicon Waveguides ◽  
Integrated Optical ◽  
Hybrid Devices ◽  
Optical Circuits ◽  
Integrated Optical Circuits

AbstractActive Silicon integrated Optical Circuits (ASOC™) is a technology based on single-mode rib waveguides formed on silicon-on-insulator that is being used to manufacture commercial integrated optics components. Silicon waveguides have excellent properties for many applications in the 1.3 and 1.55 micron telecommunications bands including relatively low loss. An important aspect of ASOC™ technology is the development of a set of waveguide-based elements that can be assembled into practical integrated optics devices. The fundamental waveguide elements include bends, couplers and fiber-waveguide interfaces, and additional elements include doped structures and waveguide gratings. Discrete lasers and photodetectors are also incorporated into ASOC™ technology to form hybrid devices. The technology is being used to manufacture devices for applications in telecomunications and optical sensing, the first major product being a two-wavelength single-fiber bi-directional optical transceiver.

Integrated Optical Circuits

1991 ◽  
pp. 1-12
Author(s):  
Norazan Mohd Kassim
Keyword(s):  
Integrated Optics ◽  
Optical Waveguides ◽  
Loss Mechanism ◽  
Integrated Optical ◽  
Optical Circuits ◽  
Integrated Optical Waveguides ◽  
Integrated Optical Circuits

This paper decribes in detail the material and fabrication procees demonstrated for integrated optics application.The loss mechanism of integrated optical waveguides are also dicused.

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

Transport Properties Of Metallic Nanowires On Silicon Substrate

2014 ◽  
Vol 2 (1) ◽  
pp. 20-23
Author(s):  
Jaskiran Kaur ◽  
◽  
Surinder Singh ◽  
Keyword(s):  
Transport Properties ◽  
Silicon Substrate ◽  
Metallic Nanowires

Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Silicon Substrate ◽  
Processing Technique ◽  
Electrical Characteristics ◽  
Localization Method ◽  
The Right ◽  
Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

Studies on a Novel Qualification Method of Silicon Nitride Layer

2016 ◽  
Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Silicon Substrate ◽  
Nitride Layer ◽  
Passivation Layer ◽  
Wafer Fabrication ◽  
Wafer Surface ◽  
Si3n4 Layer ◽  
Silicon Nitride Layer ◽  
Passivation Layers ◽  
Pinhole Test

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

Sign in / Sign up

Export Citation Format

Share Document