Detection and repair of radiation induced single event upsets in an FPGA-based readout for TES bolometer arrays

Study of single event upsets (SEUS) a survey and analysis

10.32920/ryerson.14652159 ◽

2021 ◽

Author(s):

Sheldon Mark Foulds

Keyword(s):

Error Control ◽

Hamming Code ◽

Single Event ◽

Electronic Circuits ◽

Error Control Coding ◽

Computing Systems ◽

Single Event Upsets ◽

Triple Modular Redundancy ◽

Radiation Induced ◽

Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

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Impact of Single-Event Upsets in Deep-Submicron Silicon Technology

MRS Bulletin ◽

10.1557/mrs2003.38 ◽

2003 ◽

Vol 28 (2) ◽

pp. 117-120 ◽

Cited By ~ 15

Author(s):

Robert Baumann

Keyword(s):

Soft Errors ◽

Deep Submicron ◽

Soft Error ◽

Mitigation Strategies ◽

Single Event ◽

Radiation Mechanisms ◽

Silicon Technology ◽

Single Event Upsets ◽

Radiation Induced ◽

Considerable Concern

AbstractThe once-ephemeral soft error phenomenon has recently caused considerable concern for manufacturers of advanced silicon technology. Soft errors, if unchecked, now have the potential for inducing a higher failure rate than all of the other reliability-failure mechanisms combined. This article briefly reviews the three dominant radiation mechanisms responsible for soft errors in terrestrial applications and how soft errors are generated by the collection of radiation-induced charge. Scaling trends in the soft error sensitivity of various memory and logic components are presented, along with a consideration of which applications are most likely to require intervention. Some of the mitigation strategies that can be employed to reduce the soft error rate in these devices are also discussed.

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Protecting Image Processing Pipelines against Configuration Memory Errors in SRAM-Based FPGAs

Electronics ◽

10.3390/electronics7110322 ◽

2018 ◽

Vol 7 (11) ◽

pp. 322 ◽

Cited By ~ 1

Author(s):

Luis Aranda ◽

Pedro Reviriego ◽

Juan Maestro

Keyword(s):

Image Processing ◽

Single Event ◽

Image Processing Algorithm ◽

Memory Errors ◽

Space Applications ◽

Single Event Upsets ◽

Error Mitigation ◽

Speed Up ◽

Radiation Induced ◽

Novel Method

Image processing systems are widely used in space applications, so different radiation-induced malfunctions may occur in the system depending on the device that is implementing the algorithm. SRAM-based FPGAs are commonly used to speed up the image processing algorithm, but then the system could be vulnerable to configuration memory errors caused by single event upsets (SEUs). In those systems, the captured image is streamed pixel by pixel from the camera to the FPGA. Certain local operations such as median or rank filters need to process the image locally instead of pixel by pixel, so some particular pixel caching structures such as line-buffer-based pipelines can be used to accelerate the filtering process. However, an SRAM-based FPGA implementation of these pipelines may have malfunctions due to the mentioned configuration memory errors, so an error mitigation technique is required. In this paper, a novel method to protect line-buffer-based pipelines against SRAM-based FPGA configuration memory errors is presented. Experimental results show that, using our protection technique, considerable savings in terms of FPGA resources can be achieved while maintaining the SEU protection coverage provided by other classic pipeline protection schemes.

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Study of single event upsets (SEUS) a survey and analysis

10.32920/ryerson.14652159.v1 ◽

2021 ◽

Author(s):

Sheldon Mark Foulds

Keyword(s):

Error Control ◽

Hamming Code ◽

Single Event ◽

Electronic Circuits ◽

Error Control Coding ◽

Computing Systems ◽

Single Event Upsets ◽

Triple Modular Redundancy ◽

Radiation Induced ◽

Modular Redundancy

Over the last few years evolution in electronics technology has led to the shrinkage of electronic circuits. While this has led to the emergence of more powerful computing systems it has also caused a dramatic increase in the occurrence of soft errors and a steady climb in failure in time (FIT) rates. This problem is most prevalent in FPGA based systems which are highly susceptible to radiation induced errors. Depending upon the severity of the problem a number of methods exist to counter these effects including Triple Modular Redundancy (TMR), Error Control Coding (ECC), scrubbing systems etc. The following project presents a simulation of an FPGA based system that employs one of the popular error control code techniques called the Hamming Code. A resulting analysis shows that Hamming Code is able to mitigate the effects of single event upsets (SEUs) but suffers due to a number of limitations.

Download Full-text