Optoelectronic Integrated Circuits For High Speed Signal Processing

1986 ◽  
Vol 25 (10) ◽  
Author(s):  
M. K. Kilcoyne ◽  
S. Beccue ◽  
K. D. Pedrotti ◽  
R. Asatourian ◽  
R. Anderson
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
High Speed ◽  
Optoelectronic Integrated Circuits

scholarly journals In-Plane Detection of Guided Surface Plasmons for High-Speed Optoelectronic Integrated Circuits

2017 ◽  
Vol 3 (1) ◽  
pp. 1700196 ◽  
Author(s):  
Evgeniy Panchenko ◽  
Jasper J. Cadusch ◽  
Ori Avayu ◽  
Tal Ellenbogen ◽  
Timothy D. James ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Surface Plasmons ◽  
High Speed ◽  
Optoelectronic Integrated Circuits

scholarly journals Design of High-Speed Low Power Computational Blocks for DSP Processors

2021 ◽  
Vol 11 (2) ◽  
pp. 1419-1429
Author(s):  
Alivelu Manga N.
Keyword(s):  
Signal Processing ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Large Scale ◽  
Power Optimization ◽  
Digital Signal ◽  
Oxide Semiconductor ◽  
Performance Criteria

In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

InP-HBT ICs FOR 40 Gb/s OPTICAL LINKS

1998 ◽  
Vol 09 (02) ◽  
pp. 595-630
Author(s):  
MEHRAN MOKHTARI ◽  
URBAN WESTERGREN ◽  
BO WILLÉN ◽  
THOMAS SWAHN ◽  
ROBERT WALDEN
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Optical Transmission ◽  
Supply Voltage ◽  
Measurement Equipment ◽  
Optical Links ◽  
Optoelectronic Integrated Circuits ◽  
Fiber Optical ◽  
Strong Candidate ◽  
Electronic Parts

InP-based HBT technology has proven to be a strong candidate for ultra high speed electronic as well as optoelectronic integrated circuits. The cut-offs frequencies of the available devices exceed 100 GHz. To challenge the technology, a variety of circuits, suitable for a demonstrator for the 40 Gb/s fiber optical transmission system have been designed, fabricated, and tested. All the circuits show potential for 40 Gb/s applications. The electrical parts have been implemented in MSI/LSI AlInAs/InGaAs-HBT technology, while the monolithic optoelectronic receivers were realized in SSI- InP/InGaAs HBT technology. The verification of performance of the circuits have been mainly limited by available measurement equipment. All the electronic parts were operational with 3 volt supply voltage. All the circuits were fully functional after the first processing round. No redesign was necessary.

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