Implementation of neural network hardware based on a floating point operation in an FPGA

2007 ◽  
Author(s):  
Jeong-Seob Kim ◽  
Seul Jung
Keyword(s):  
Neural Network ◽  
Floating Point ◽  
Neural Network Hardware

scholarly journals AHEAD: Automatic Holistic Energy-Aware Design Methodology for MLP Neural Network Hardware Generation in Proactive BMI Edge Devices

Energies ◽  
2020 ◽  
Vol 13 (9) ◽  
pp. 2180
Author(s):  
Nan-Sheng Huang ◽  
Yi-Chung Chen ◽  
Jørgen Christian Larsen ◽  
Poramate Manoonpong
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Design Methodology ◽  
Hardware Design ◽  
Design Flow ◽  
Floating Point ◽  
Energy Aware ◽  
Mlp Neural Network ◽  
Neural Recordings ◽  
Neural Network Hardware

The prediction of a high-level cognitive function based on a proactive brain–machine interface (BMI) control edge device is an emerging technology for improving the quality of life for disabled people. However, maintaining the stability of multiunit neural recordings is made difficult by the nonstationary nature of neurons and can affect the overall performance of proactive BMI control. Thus, it requires regular recalibration to retrain a neural network decoder for proactive control. However, retraining may lead to changes in the network parameters, such as the network topology. In terms of the hardware implementation of the neural decoder for real-time and low-power processing, it takes time to modify or redesign the hardware accelerator. Consequently, handling the engineering change of the low-power hardware design requires substantial human resources and time. To address this design challenge, this work proposes AHEAD: an automatic holistic energy-aware design methodology for multilayer perceptron (MLP) neural network hardware generation in proactive BMI edge devices. By taking a holistic analysis of the proactive BMI design flow, the approach makes judicious use of the intelligent bit-width identification (BWID) and configurable hardware generation, which autonomously integrate to generate the low-power hardware decoder. The proposed AHEAD methodology begins with the trained MLP parameters and golden datasets and produces an efficient hardware design in terms of performance, power, and area (PPA) with the least loss of accuracy. The results show that the proposed methodology is up to a 4X faster in performance, 3X lower in terms of power consumption, and achieves a 5X reduction in area resources, with exact accuracy, compared to floating-point and half-floating-point design on a field-programmable gate array (FPGA), which makes it a promising design methodology for proactive BMI edge devices.

Wafer‐Scale 2D Hafnium Diselenide Based Memristor Crossbar Array for Energy‐Efficient Neural Network Hardware

2021 ◽  
pp. 2103376 ◽  
Author(s):  
Sifan Li ◽  
Mei‐Er Pam ◽  
Yesheng Li ◽  
Li Chen ◽  
Yu‐Chieh Chien ◽  
...  
Keyword(s):  
Neural Network ◽  
Energy Efficient ◽  
Wafer Scale ◽  
Crossbar Array ◽  
Neural Network Hardware ◽  
Memristor Crossbar

Surrogate Model based Co-Optimization of Deep Neural Network Hardware Accelerators

2021 ◽  
Author(s):  
Hendrik Wohrle ◽  
Mariela De Lucas Alvarez ◽  
Fabian Schlenke ◽  
Alexander Walsemann ◽  
Michael Karagounis ◽  
...  
Keyword(s):  
Neural Network ◽  
Surrogate Model ◽  
Deep Neural Network ◽  
Hardware Accelerators ◽  
Model Based ◽  
Neural Network Hardware

scholarly journals A Quantized CNN-Based Microfluidic Lensless-Sensing Mobile Blood-Acquisition and Analysis System

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5103 ◽  
Author(s):  
Liao ◽  
Yu ◽  
Tian ◽  
Li ◽  
Li
Keyword(s):  
Neural Network ◽  
Group Structure ◽  
Image Acquisition ◽  
Cell Segmentation ◽  
Floating Point ◽  
Prototype System ◽  
Processing Efficiency ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Analysis System

This paper proposes a microfluidic lensless-sensing mobile blood-acquisition and analysis system. For a better tradeoff between accuracy and hardware cost, an integer-only quantization algorithm is proposed. Compared with floating-point inference, the proposed quantization algorithm makes a tradeoff that enables miniaturization while maintaining high accuracy. The quantization algorithm allows the convolutional neural network (CNN) inference to be carried out using integer arithmetic and facilitates hardware implementation with area and power savings. A dual configuration register group structure is also proposed to reduce the interval idle time between every neural network layer in order to improve the CNN processing efficiency. We designed a CNN accelerator architecture for the integer-only quantization algorithm and the dual configuration register group and implemented them in field-programmable gate arrays (FPGA). A microfluidic chip and mobile lensless sensing cell image acquisition device were also developed, then combined with the CNN accelerator to build the mobile lensless microfluidic blood image-acquisition and analysis prototype system. We applied the cell segmentation and cell classification CNN in the system and the classification accuracy reached 98.44%. Compared with the floating-point method, the accuracy dropped by only 0.56%, but the area decreased by 45%. When the system is implemented with the maximum frequency of 100 MHz in the FPGA, a classification speed of 17.9 frames per second (fps) can be obtained. The results show that the quantized CNN microfluidic lensless-sensing blood-acquisition and analysis system fully meets the needs of current portable medical devices, and is conducive to promoting the transformation of artificial intelligence (AI)-based blood cell acquisition and analysis work from large servers to portable cell analysis devices, facilitating rapid early analysis of diseases.

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