scholarly journals A Quantized CNN-Based Microfluidic Lensless-Sensing Mobile Blood-Acquisition and Analysis System

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5103 ◽  
Author(s):  
Liao ◽  
Yu ◽  
Tian ◽  
Li ◽  
Li
Keyword(s):  
Neural Network ◽  
Group Structure ◽  
Image Acquisition ◽  
Cell Segmentation ◽  
Floating Point ◽  
Prototype System ◽  
Processing Efficiency ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Analysis System

This paper proposes a microfluidic lensless-sensing mobile blood-acquisition and analysis system. For a better tradeoff between accuracy and hardware cost, an integer-only quantization algorithm is proposed. Compared with floating-point inference, the proposed quantization algorithm makes a tradeoff that enables miniaturization while maintaining high accuracy. The quantization algorithm allows the convolutional neural network (CNN) inference to be carried out using integer arithmetic and facilitates hardware implementation with area and power savings. A dual configuration register group structure is also proposed to reduce the interval idle time between every neural network layer in order to improve the CNN processing efficiency. We designed a CNN accelerator architecture for the integer-only quantization algorithm and the dual configuration register group and implemented them in field-programmable gate arrays (FPGA). A microfluidic chip and mobile lensless sensing cell image acquisition device were also developed, then combined with the CNN accelerator to build the mobile lensless microfluidic blood image-acquisition and analysis prototype system. We applied the cell segmentation and cell classification CNN in the system and the classification accuracy reached 98.44%. Compared with the floating-point method, the accuracy dropped by only 0.56%, but the area decreased by 45%. When the system is implemented with the maximum frequency of 100 MHz in the FPGA, a classification speed of 17.9 frames per second (fps) can be obtained. The results show that the quantized CNN microfluidic lensless-sensing blood-acquisition and analysis system fully meets the needs of current portable medical devices, and is conducive to promoting the transformation of artificial intelligence (AI)-based blood cell acquisition and analysis work from large servers to portable cell analysis devices, facilitating rapid early analysis of diseases.

scholarly journals Pattern Classification of Fabric Defects Using a Probabilistic Neural Network and Its Hardware Implementation using the Field Programmable Gate Array System

2017 ◽  
Vol 25 (0) ◽  
pp. 42-48 ◽  
Author(s):  
Abul Hasnat ◽  
Anindya Ghosh ◽  
Amina Khatun ◽  
Santanu Halder
Keyword(s):  
Neural Network ◽  
Hardware Implementation ◽  
Probabilistic Neural Network ◽  
Clock Period ◽  
Data Set ◽  
Gate Arrays ◽  
Hardware System ◽  
Field Programmable ◽  
Programmable Gate Arrays

This study proposes a fabric defect classification system using a Probabilistic Neural Network (PNN) and its hardware implementation using a Field Programmable Gate Arrays (FPGA) based system. The PNN classifier achieves an accuracy of 98 ± 2% for the test data set, whereas the FPGA based hardware system of the PNN classifier realises about 94±2% testing accuracy. The FPGA system operates as fast as 50.777 MHz, corresponding to a clock period of 19.694 ns.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

scholarly journals Design and Implementation of Perceptron Neuron in Machine Learning for Handwritten Character Recognition

2020 ◽  
Vol 9 (10) ◽  
pp. 357-363
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Feature Extraction ◽  
Field Programmable Gate Arrays ◽  
Fpga Implementation ◽  
Floating Point ◽  
Neuron Network ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Due to the exponential increase of electronic devices that are connected to the Internet, the amount of data that they produce have grown to the same extent. In order to face the processing of these data, the use of some automatic learning algorithms, also known as Machine Learning, has become widespread. The most popular is the one known as neural networks. These algorithms need a great deal of resources to compute all their operations, and because of that, they have been traditionally implemented in application specific integrated circuits. However, recently there have been a boom in implementations in field programmable gate arrays, also known as FPGAs. These allow greater parallelism in the implementation of the algorithms. Field Programmable Gate Arrays (FPGA) implementation based feature extraction method is proposed in this paper. This particular application is handwritten offline digit recognition. The classification depends on simple 2 layer MultiLayer Perceptron (MLP). The particular feature extraction approach is suitable for execution of FPGA because it is utilized with subtraction and addition operations. From Standard database handwritten digit images of normalized 40×40 pixel the features are extracted by the proposed method. It has been discovered by experiential outcomes that 85% accuracy is achieved by proposed system. Overall, as compared to other systems, it is less complex, more accurate and simple. Further this project explains IEE-754 format single precision floating point MAC unit’s FPGA implementation which is utilized for feeding the neurons weighted inputs in artificial neural networks. Data representation range is improved by floating point numbers utilization to a higher number from smaller number that is highly suggested for Artificial Neuron Network. The code is developed in HDL, simulated and synthesis results are extracted using Xilinx synthesis tools .In order to validate its computational accuracy of the FFT, an MATLAB validation script is used to verify the output of HDL with standard reference model.

Design of a Tritium-In-Air Monitor Using Field-Programmable Gate Arrays

2016 ◽  
Vol 2 (4) ◽  
Author(s):  
Phillip McNelles ◽  
Lixuan Lu
Keyword(s):  
Nuclear Power ◽  
Power Plants ◽  
Noble Gas ◽  
Field Programmable Gate Arrays ◽  
Radiation Detectors ◽  
Prototype System ◽  
Carbon 14 ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field including instrumentation and control (I&C) systems, pulse measurement systems, particle detectors, and health physics. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to increased production of tritium, which poses a health risk and must be monitored by tritium-in-air monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of carbon-14 and the addition of noble-gas compensation, are incorporated into a new FPGA-based TAM along with the standard functions included in the original microprocessor-based TAM. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. Potential issues caused by radiation interactions with the FPGA are beyond the scope of this work.

scholarly journals An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

2021 ◽  
Vol 2089 (1) ◽  
pp. 012069
Author(s):  
A. Pradeep kumar ◽  
Y. Devendar Reddy ◽  
T. Srinivas Reddy ◽  
K. Jamal
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Heavy Traffic ◽  
Data Traffic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Hardware Costs

Abstract Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

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