A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies

2005 ◽  
Author(s):  
Adrian Estrada ◽  
Carlos J. Jimenez ◽  
Manuel Valencia
Keyword(s):  
Deep Submicron ◽  
Arithmetic Circuits

dC/dV and CV Characterization of Gate Resistance Defects in eDRAM Circuits

2013 ◽  
Author(s):  
Sweta Pendyala ◽  
Dave Albert ◽  
Katherine Hawkins ◽  
Michael Tenney
Keyword(s):  
Deep Submicron ◽  
Work Flow ◽  
Localization Technique ◽  
Characterization Techniques ◽  
Capacitance Voltage ◽  
Gate Resistance

Abstract Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

Characterization of Long Wire Data Leakage in Deep Submicron FPGAs

2019 ◽  
Author(s):  
George Provelengios ◽  
Chethan Ramesh ◽  
Shivukumar B. Patil ◽  
Ken Eguro ◽  
Russell Tessier ◽  
...  
Keyword(s):  
Deep Submicron

New Mechanisms and the Characterization of Plasma Charging Enhanced Hot Carrier Effect in Deep-Submicron N-MOSFET's

2000 ◽  
Author(s):  
S. J. Chen ◽  
H. L. Kao ◽  
Steve S. Chung ◽  
C. C. Chen ◽  
C. Y. Chang ◽  
...  
Keyword(s):  
Deep Submicron ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Hot Carrier Effect

scholarly journals Accuracy and Physical Characterization of Approximate Arithmetic Circuits

2020 ◽  
Author(s):  
Daniela Catelan ◽  
Ricardo Santos ◽  
Liana Duenha
Keyword(s):  
Power Dissipation ◽  
Power Efficiency ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Accuracy Control ◽  
Field Programmable ◽  
Speed Up ◽  
Circuit Techniques ◽  
The Cost

With the end of Dennard's scale, designers have been looking for new alternatives and approximate computing (AC) has managed to attract the attention of researchers, by offering techniques ranging from the application level to the circuit level. When applying approximate circuit techniques in hardware design, the program user may speed up the application while a designer may save area and power dissipation at the cost of less accuracy on the operations results. This paper discusses the compromise between accuracy versus physical efficiency by presenting a set of experiments and results of tailor-made approximate arithmetic circuits on Field-Programmable Gate Array (FPGA) platforms. Our results reveal that an approximate circuit with accuracy control could not be useful if the goal is to save circuit area or even power dissipation. Even for circuits that seem to have power efficiency, we should care about the size and prototyping platform where the hardware will be used.

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