Ring oscillator behavior after oxide breakdown

2005 ◽  
Author(s):  
R. Fernandez ◽  
R. Rodriguez ◽  
M. Nafria ◽  
X. Aymerich
Keyword(s):  
Ring Oscillator ◽  
Oxide Breakdown

A Study of Pad Contamination Defect and Removal

2008 ◽  
Author(s):  
K.A. Mohammad ◽  
L.J. Liu ◽  
S.F. Liew ◽  
S.F. Chong ◽  
D.G. Lee ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Gate Oxide ◽  
Action Plans ◽  
Preventive Action ◽  
Oxide Breakdown ◽  
Reliability Level ◽  
The Future ◽  
Dry Etch ◽  
Removal Technique

Abstract The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Fundamental Considerations for CDM Failure in 90nm Products

2006 ◽  
Author(s):  
Nobuyuki Wakai ◽  
Yuji Kobira ◽  
Hidemitsu Egawa ◽  
Masayoshi Tsutsumi
Keyword(s):  
Breakdown Voltage ◽  
High Speed ◽  
Gate Oxide ◽  
Critical Parameters ◽  
Protection Device ◽  
Oxide Breakdown ◽  
Technology Products ◽  
Charged Device ◽  
Device Size ◽  
Fundamental Consideration

Abstract Fundamental consideration for CDM (Charged Device Model) breakdown was investigated with 90nm technology products and others. According to the result of failure analysis, it was found that gate oxide breakdown was critical failure mode for CDM test. High speed triggered protection device such as ggNMOS and SCR (Thyristor) is effective method to improve its CDM breakdown voltage and an improvement for evaluated products were confirmed. Technological progress which is consisted of down-scaling of protection device size and huge number of IC pins of high function package makes technology vulnerable and causes significant CDM stress. Therefore, it is expected that CDM protection designing tends to become quite difficult. In order to solve these problems in the product, fundamental evaluations were performed. Those are a measurement of discharge parameter and stress time dependence of CDM breakdown voltage. Peak intensity and rise time of discharge current as critical parameters are well correlated their package capacitance. Increasing stress time causes breakdown voltage decreasing. This mechanism is similar to that of TDDB for gate oxide breakdown. Results from experiences and considerations for future CDM reliable designing are explained in this report.

Single Point PICA Probing with an Avalanche Photo-Diode

2001 ◽  
Author(s):  
Mike Bruce ◽  
Rama R. Goruganthu ◽  
Shawn McBride ◽  
David Bethke ◽  
J.M. Chin
Keyword(s):  
Single Photon ◽  
Single Point ◽  
Photon Counting ◽  
Ring Oscillator ◽  
Time Resolved ◽  
Single Photon Counting ◽  
Photo Diode ◽  
Avalanche Photo Diode ◽  
Photo Multiplier Tube ◽  
Channel Plate

Abstract For time resolved hot carrier emission from the backside, an alternate approach is demonstrated termed single point PICA. The single point approach records time resolved emission from an individual transistor using time-correlated-single-photon counting and an avalanche photo-diode. The avalanche photo-diode has a much higher quantum efficiency than micro-channel plate photo-multiplier tube based imaging cameras typically used in earlier approaches. The basic system is described and demonstrated from the backside on a ring oscillator circuit.

Application of Novel Low Current OBIRCH Amplifier and Nanoprobing to Identify Subtle Leakages in Advanced Node Technologies

2018 ◽  
Author(s):  
Satish Kodali ◽  
Liangshan Chen ◽  
Yuting Wei ◽  
Tanya Schaeffer ◽  
Chong Khiam Oh
Keyword(s):  
Signal To Noise Ratio ◽  
Semiconductor Industry ◽  
Fault Isolation ◽  
Ring Oscillator ◽  
High Signal ◽  
The Novel ◽  
Resistance Change ◽  
Three Samples ◽  
Relative Threshold ◽  
First Time

Abstract Optical beam induced resistance change (OBIRCH) is a very well-adapted technique for static fault isolation in the semiconductor industry. Novel low current OBIRCH amplifier is used to facilitate safe test condition requirements for advanced nodes. This paper shows the differences between the earlier and novel generation OBIRCH amplifiers. Ring oscillator high standby leakage samples are analyzed using the novel generation amplifier. High signal to noise ratio at applied low bias and current levels on device under test are shown on various samples. Further, a metric to demonstrate the SNR to device performance is also discussed. OBIRCH analysis is performed on all the three samples for nanoprobing of, and physical characterization on, the leakage. The resulting spots were calibrated and classified. It is noted that the calibration metric can be successfully used for the first time to estimate the relative threshold voltage of individual transistors in advanced process nodes.

Laser Silicon Interaction Study on Ring Oscillators to Establish Temperature Voltage Dependency Trends on 14 nm and Future FinFET Technologies

2017 ◽  
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan
Keyword(s):  
High Speed ◽  
Laser Frequency ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Dual Nature ◽  
Voltage Imaging ◽  
Multiple Cores ◽  
Speed Performance ◽  
Self Test ◽  
Frequency Changes

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.

Backside FIB Device Modifications Through the BOX Layer of an SOI Device

2002 ◽  
Author(s):  
Jeffery P. Huynh ◽  
Joseph P. Shannon ◽  
Richard W. Johnson ◽  
Mike Santana ◽  
Thomas Y. Chu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Oxide Layer ◽  
Cross Section ◽  
Test Structure ◽  
Ring Oscillator ◽  
Oscillator Circuit ◽  
Entire Process ◽  
Oscillator Frequency ◽  
Polysilicon Gate ◽  
Resistance Data

Abstract Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

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