A 2V 0.35μm CMOS DECT RF front end with on-chip frequency synthesizer

2005 ◽  
Author(s):  
D. Guermandi ◽  
E. Franchi ◽  
A. Gnudi ◽  
P. Rossi ◽  
F. Svelto ◽  
...  
2006 ◽  
Vol 41 (2) ◽  
pp. 384-394 ◽  
Author(s):  
P. Sivonen ◽  
J. Tervaluoto ◽  
N. Mikkola ◽  
A. Parssinen

2015 ◽  
Vol 3 (4) ◽  
pp. 361-364 ◽  
Author(s):  
Ji Liang ◽  
Hongxiang Zhang ◽  
Daihua Zhang ◽  
Hao Zhang ◽  
Wei Pang

Sensors ◽  
2018 ◽  
Vol 18 (2) ◽  
pp. 110 ◽  
Author(s):  
Massimo Merenda ◽  
Corrado Felini ◽  
Francesco Della Corte
Keyword(s):  

Author(s):  
MANJULA. K ◽  
PRATHIBHA. S. K

In this paper, A Software-Defined Radio (SDR) RF front-end is presented that contains merged LNA and mixers, VGAs, and frequency synthesizer, supporting various wireless communication standards in 0.1-2 GHz while guaranteeing a power/performance trade-off at any time. The proposed low power RF front-end uses the folded and current reuse techniques. for 0.18 um RF CMOS technology with 1.8V supply voltage. In the receive path the proposed design achieves a Noise Figure of 3.8 dB at 160 MHz and 5.5 dB at 2GHz. The Output-referred 3rd-order Intercept Point (OIP3) is high up to 21.3 dBm at 800 MHz. The voltage gain of the front- end is between 16-44 dB. The phase mismatch of LO quadrature signals is lower than 3deg.It consumes 13.8 mW at the 1.7V supply.


2011 ◽  
Vol 32 (9) ◽  
pp. 095004
Author(s):  
Hua Xu ◽  
Lei Wang ◽  
Yin Shi ◽  
Fa Foster Dai

2002 ◽  
Vol 25 (1) ◽  
pp. 23-46
Author(s):  
Ptros S. Tsenes ◽  
Giorgos E. Stratakos ◽  
Nikolaos K. Uzunoglu

In this paper two active MMIC mixers for RF front-end applications are described. A down-converter that converts an RF signal(fRF=10.45 GHz)into an IF signal(fIF=0.95 GHz)using an LO signal(fLO=9.5 GHz)and an up-converter that performs the opposite process have been fabricated. The down-converter is designed using the topology of a dual-gate pHEMT, while the up-converter is implemented in the form of a double balanced mixer using the topology of the Gilbert cell and the occupied areas are approximately0.78 mm2and3.86 mm2, respectively. Both mixers present conversion gain, very low input and output return losses, very good isolation between all of their ports and the required LO power is quite low, while the up-converter contains on chip, except for the dc-bias and matching sub-circuits, the required LO and RF baluns. Both circuits have been fabricated using the H-40 process of GEC-Marconi. Section 1 presents fundamentals on mixer theory and mixer design while in Section 2 the characteristics of H-40 process are described. In Section 3 and in Section 4 the designing, the simulated and the measured results of the down-converter and the up-converter are presented, respectively.


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