scholarly journals High-performance VLSI architecture for video processing

2003 ◽  
Author(s):  
Hector Navarro ◽  
Juan A. Montiel-Nelson ◽  
Javier Sosa ◽  
Jose C. Garcia ◽  
Roberto Sarmiento ◽  
...  
Keyword(s):  
Video Processing ◽  
High Performance ◽  
Vlsi Architecture

I-DMAC: An Intelligent DMA Controller for Utilization - Aware Video Streaming used in AI Applications

2021 ◽  
pp. 60-70
Author(s):  
Piyush Kumar Shukla ◽  
◽  
Prashant Kumar Shukla ◽  
Keyword(s):  
Video Processing ◽  
High Performance ◽  
Data Transfer ◽  
Direct Memory Access ◽  
Large Data ◽  
Video Frame ◽  
Microprocessor System ◽  
Bulk Data ◽  
Xilinx Fpga ◽  
Vhdl Code

The interpretation of large data streams necessitates high-performance repeated transfers, which overload Microprocessor System on Chips (SoC). The effective direct memory access (DMA) controller performs bulk data transfers without the CPU's involvement. The Direct Memory Controller (DMAC) solves this by facilitating bulk data transfer and execution. In this work, we created an intelligent DMAC (I-DMAC) for accessing video processing data without using CPUs. The model includes Bus selection Module, User control signal, Status Register, DMA supported Address, and AXI-PCI subsystems for improved video frame analysis. These modules are experimentally verified in Xilinx FPGA SoC architecture using VHDL code simulation and results compared to the E-DMAC model.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

High-performance VLSI architecture for traffic sign detection

2018 ◽  
Vol 47 (9) ◽  
pp. 926001 ◽  
Author(s):  
王刚毅 Wang Gangyi ◽  
金炎胜 Jin Yansheng ◽  
任广辉 Ren Guanghui ◽  
刘 通 Liu Tong
Keyword(s):  
High Performance ◽  
Vlsi Architecture ◽  
Traffic Sign ◽  
Sign Detection ◽  
Traffic Sign Detection

Low-Cost Image and Video Processing Using High-Performance Middleware in Single-board Computers with Open Internet Standards

2020 ◽  
Vol 18 (02) ◽  
pp. 311-318
Author(s):  
Carlos Alejandro Perez ◽  
Mario Sergio Cleva ◽  
Diego Orlando Liska ◽  
Dominga Concepcion Aquino ◽  
Claudio Rodrigues da Fonseca
Keyword(s):  
Video Processing ◽  
High Performance ◽  
Low Cost ◽  
Image And Video Processing

Hardware acceleration of lucky-region fusion (LRF) algorithm for high-performance real-time video processing

2015 ◽  
Author(s):  
Tyler Browning ◽  
Christopher Jackson ◽  
Furkan Cayci ◽  
Gary W. Carhart ◽  
J. J. Liu ◽  
...  
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Performance ◽  
Hardware Acceleration
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