A high-performance VLSI architecture for advanced encryption standard (AES) algorithm

2006 ◽  
Author(s):  
N.M. Kosaraju ◽  
M. Varanasi ◽  
S.P. Mohanty
Keyword(s):  
High Performance ◽  
Vlsi Architecture ◽  
Advanced Encryption Standard ◽  
Aes Algorithm

scholarly journals Generating Cipher Text using BLOWFISH Algorithm for Secured Data Communications

2019 ◽  
Vol 9 (2) ◽  
pp. 117-121
Keyword(s):  
High Speed ◽  
High Performance ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Aes Algorithm ◽  
Cipher Text ◽  
Original Message ◽  
Public Domain Software ◽  
Secured Data ◽  
Vhdl Code

Cryptography plays a major role in the network security. In order to secure the data one must do encryption of the original message. In this paper, the design and analysis of high speed and high performance BLOWFISH algorithm is implemented in VHDL coding and compared with AES (Advanced Encryption Standard) algorithm. The BLOWFISH algorithm involves the process of giving the data and key as input to the encryption block. BLOWFISH encryption algorithm is designed and programmed in VHDL coding. Then it is implemented in Xilinx 10.1. This research is carried in the following steps: designing of encryption algorithm, writing VHDL code, simulating the code on “ModelSim altera 6.5e”, synthesizing and implementing the code using Xilinx’s ISE 10.1.This research aims in developing flexible and technology independent architectures in the areas of VPN software, file compression, public domain software such as smart cards, etc. Also presents the comparison of BLOWFISH and AES algorithms. Experimental results show that BLOWFISH algorithm runs faster than AES algorithm while both of them consume almost the same Power.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

scholarly journals Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽  
2019 ◽  
Author(s):  
Luka Daoud ◽  
Fady Hussein ◽  
Nader Rafla
Keyword(s):  
High Level Synthesis ◽  
Advanced Encryption Standard ◽  
Data Confidentiality ◽  
Maximum Throughput ◽  
Loop Unrolling ◽  
Aes Algorithm ◽  
Hardware Implementations ◽  
High Level ◽  
Dedicated Hardware ◽  
Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

AES Enhanced by Output Feedback Block Mode Operation

2020 ◽  
Vol 1 (1) ◽  
pp. 11-22
Author(s):  
Asaad A. Hani
Keyword(s):  
Output Feedback ◽  
Data Security ◽  
New Technology ◽  
Advanced Encryption Standard ◽  
The Internet ◽  
Secret Key ◽  
Aes Algorithm ◽  
Mode Operation ◽  
Federal Information Processing Standard ◽  
Exclusive Or

There is a great research in the field of data security these days. Storing information digitally in the cloud and transferring it over the internet proposes risks of disclosure and unauthorized access; thus, users, organizations, and businesses are adapting new technology and methods to protect their data from breaches. In this paper, we introduce a method to provide higher security for data transferred over the internet, or information based in the cloud. The introduced method for the most part depends on the Advanced Encryption Standard (AES) algorithm, which is currently the standard for secret key encryption. A standardized version of the algorithm was used by The Federal Information Processing Standard 197 called Rijndael for the AES. The AES algorithm processes data through a combination of exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and MixColumn operations. The fact that the algorithm could be easily implemented and run on a regular computer in a reasonable amount of time made it highly favorable and successful. In this paper, the proposed method provides a new dimension of security to the AES algorithm by securing the key itself such that even when the key is disclosed; the text cannot be deciphered. This is done by enciphering the key using Output Feedback Block Mode Operation. This introduces a new level of security to the key in a way, in which deciphering the data requires prior knowledge of the key and the algorithm used to encipher the key for the purpose of deciphering the transferred text.

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