Optimization of EDP solutions for feature size independent silicon etching

2003 ◽  
Author(s):  
Chandana Yellampalli ◽  
Kunchinadka N. Bhat ◽  
Nandita DasGupta ◽  
Amitava DasGupta ◽  
Parimi R. Rao
Keyword(s):  
Silicon Etching ◽  
Feature Size

Optimization of EDP solutions for feature-size-independent silicon etching

2001 ◽  
Author(s):  
Kunchinadka N. Bhat ◽  
Chandana Yellempalle ◽  
Nandita DasGupta ◽  
Amitava DasGupta ◽  
Parimi R. Rao
Keyword(s):  
Silicon Etching ◽  
Feature Size

A New Approach for SRAM Soft Defect Root Cause Identification

2007 ◽  
Author(s):  
Peter Egger ◽  
Stefan Müller ◽  
Martin Stiftinger
Keyword(s):  
Integrated Circuits ◽  
Top Down ◽  
Feature Size ◽  
Design Rules ◽  
New Approach ◽  
Root Cause ◽  
Wafer Fab ◽  
Sram Cell ◽  
Tcad Simulation ◽  
Root Cause Identification

Abstract With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

ИССЛЕДОВАНИЕ ПРОЦЕССА ГЛУБОКОГО ТРАВЛЕНИЯ КРЕМНИЯ С МИНИМАЛЬНОЙ ШЕРОХОВАТОСТЬЮ СТЕНОК И ДНА СТРУКТУР

2020 ◽  
Vol 96 (3s) ◽  
pp. 668-675
Author(s):  
Я.А. Мирошкин
Keyword(s):  
Analytical Model ◽  
Phenomenological Description ◽  
Silicon Etching ◽  
Anisotropic Silicon Etching

Данная работа посвящена исследованию процессов глубокого анизотропного травления кремния. В качестве предложенных методов были проанализированы два подхода - Bosch и Cryo. Представлено феноменологическое описание вышеупомянутых методов, проведен анализ эксперимента по криогенному травлению кремния, полученный на базе ФТИАН, также предложена аналитическая модель Cryo-процесса. This work is devoted to the study of the processes of deep anisotropic silicon etching. Two approaches (Bosch and Cryo) have been analyzed as proposed methods. The phenomenological description of the above mentioned methods has been presented, the analysis of the experiment on cryogenic etching of silicon obtained on the basis of FTIAN has been carried out, as well as an analytical model of Cryo process has been proposed.

scholarly journals Cover Feature: Size‐Controlled Hapticity Switching in [Ln(C 9 H 9 )(C 8 H 8 )] Sandwiches (Chem. Eur. J. 54/2021)

2021 ◽  
Vol 27 (54) ◽  
pp. 13480-13480
Author(s):  
Maxime Tricoire ◽  
Luca Münzfeld ◽  
Jules Moutet ◽  
Nolwenn Mahieu ◽  
Léo La Droitte ◽  
...  
Keyword(s):  
Feature Size ◽  
Size Controlled

scholarly journals Feature Size Effect on Formability of Multilayer Metal Composite Sheets under Microscale Laser Flexible Forming

Metals ◽  
2017 ◽  
Vol 7 (7) ◽  
pp. 275 ◽  
Author(s):  
Huixia Liu ◽  
Wenhao Zhang ◽  
Jenn-Terng Gau ◽  
Zongbao Shen ◽  
Youjuan Ma ◽  
...  
Keyword(s):  
Size Effect ◽  
Metal Composite ◽  
Feature Size ◽  
Flexible Forming ◽  
Multilayer Metal

Removing W Polymer Residue from BEOL Structures Using DSP+ (Dilute Sulfuric-Peroxide-HF) Mixture – A Case Study

2012 ◽  
Vol 195 ◽  
pp. 128-131 ◽  
Author(s):  
Hun Hee Lee ◽  
Min Sang Yun ◽  
Hyun Wook Lee ◽  
Jin Goo Park
Keyword(s):  
High Speed ◽  
Semiconductor Device ◽  
Environmental Issues ◽  
Low Power Consumption ◽  
Device Performance ◽  
Metal Gate ◽  
Feature Size ◽  
High K ◽  
Removal Of Metal

As the feature size of semiconductor device shrinks continuously, various high-K metals for 3-D structures have been applied to improve the device performance, such as high speed and low power consumption. Metal gate fabrication requires the removal of metal and polymer residues after etching process without causing any undesired etching and corrosion of metals. The conventional sulfuric-peroxide mixture (SPM) has many disadvantages like the corrosion of metals, environmental issues etc., DSP+(dilute sulfuric-peroxide-HF mixture) chemical is currently used for the removal of post etch residues on device surface, to replace the conventional SPM cleaning [. Due to the increased usage of metal gate in devices in recent times, the application of DSP+chemicals for cleaning processes also increases [.

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