Diffraction analysis and evaluation of a focus-error detection scheme for an optical profilometer

2000 ◽  
Author(s):  
Chunlan Yang ◽  
Zhaobang Pu ◽  
Huijie Zhao
Keyword(s):  
Diffraction Analysis ◽  
Error Detection ◽  
Detection Scheme ◽  
Analysis And Evaluation ◽  
Optical Profilometer

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

2020 ◽  
Vol 36 (1) ◽  
pp. 33-46
Author(s):  
B. Deveautour ◽  
A. Virazel ◽  
P. Girard ◽  
V. Gherman
Keyword(s):  
Error Detection ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Detection Scheme

scholarly journals An Efficient Hardware-Based Fault-Tolerant Method for SMS4

2018 ◽  
Vol 208 ◽  
pp. 02005
Author(s):  
Hanguang Luo ◽  
Guangjun Wen ◽  
Jian Su
Keyword(s):  
Error Detection ◽  
Wireless Lan ◽  
Fault Tolerant ◽  
Low Cost ◽  
Primary Objective ◽  
Data Confidentiality ◽  
Detection Scheme ◽  
Detection Delay ◽  
Encryption Decryption ◽  
Online Error Detection

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

2007 ◽  
Vol 42 (1) ◽  
pp. 193-200 ◽  
Author(s):  
Kyu-hyoun Kim ◽  
Hoe-Ju Chung ◽  
Woo-Seop Kim ◽  
Moonsook Park ◽  
Young-Chan Jang ◽  
...  
Keyword(s):  
Error Detection ◽  
Data Rate ◽  
Detection Scheme
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