Yield enhancement based on defect reduction using on-the-fly automatic defect classification

2000 ◽  
Author(s):  
Manda Kulkarni ◽  
Andrew Skumanich
Keyword(s):  
Yield Enhancement ◽  
Defect Classification ◽  
Defect Reduction

Defect reduction in oxygen implanted silicon-on-insulator material during high-temperature annealing

1989 ◽  
Vol 47 ◽  
pp. 604-605
Author(s):  
P. Roitman ◽  
B. Cordts ◽  
S. Visitserngtrakul ◽  
S.J. Krause
Keyword(s):  
High Temperature ◽  
Annealing Temperature ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Current ◽  
Defect Reduction ◽  
Annealing Step ◽  
Multiple Cycle ◽  
Defect Densities

Synthesis of a thin, buried dielectric layer to form a silicon-on-insulator (SOI) material by high dose oxygen implantation (SIMOX – Separation by IMplanted Oxygen) is becoming an important technology due to the advent of high current (200 mA) oxygen implanters. Recently, reductions in defect densities from 109 cm−2 down to 107 cm−2 or less have been reported. They were achieved with a final high temperature annealing step (1300°C – 1400°C) in conjunction with: a) high temperature implantation or; b) channeling implantation or; c) multiple cycle implantation. However, the processes and conditions for reduction and elimination of precipitates and defects during high temperature annealing are not well understood. In this work we have studied the effect of annealing temperature on defect and precipitate reduction for SIMOX samples which were processed first with high temperature, high current implantation followed by high temperature annealing.

Defect Reduction in Ring Blank Casting Through Design of Experiments

2015 ◽  
Vol 9 (6) ◽  
pp. 536 ◽  
Author(s):  
P. Kannan ◽  
K. Balasubramanian ◽  
R. Vinayagamoorthy
Keyword(s):  
Design Of Experiments ◽  
Defect Reduction ◽  
Ring Blank

Construction of Defect Reduction System by Improving Wet-end Chemical Retention

2020 ◽  
Vol 74 (4) ◽  
pp. 309-315
Author(s):  
Hiroyuki Oishi ◽  
Koichi Tadaki ◽  
Kazutaka Kasuga
Keyword(s):  
Defect Reduction ◽  
Reduction System ◽  
Chemical Retention

Methodology to Correlate Defect Reduction Systems to Electrical Test Data via Artificially Manufactured Defects

2002 ◽  
Author(s):  
Mike Santana ◽  
Alfredo V. Herrera
Keyword(s):  
Test Data ◽  
Learning Opportunities ◽  
Inspection System ◽  
Navigation Systems ◽  
Defect Inspection ◽  
Defect Reduction ◽  
Electrical Test ◽  
Important System

Abstract This paper describes a methodology for correlating physical defect inspection/navigation systems with electrical bitmap data through the fabrication of artificial defects via reticle alterations or circuit modifications using an inline FIB. The methodology chosen consisted of altering decommissioned reticles to create defects resulting in both open and shorted circuits within areas of an AMD microprocessor cache. The reticles were subsequently scanned using a KLA SL300HR StarLight inspection system to confirm their location, while wafers processed on these reticles were scanned at several layers using standard inline metrology. Finally, the wafers were electrically tested, bitmapped, and physically deprocessed. All defect data was then analyzed and cross-correlated between each system, uncovering some important system deficiencies and learning opportunities. Data and images are included to support the significance and effectiveness of such a methodology.

ATE Failure Isolation Methodologies for Failure Analysis, Design Debug and Yield Enhancement

1998 ◽  
Author(s):  
D.S. Patrick ◽  
L.C. Wagner ◽  
P.T. Nguyen
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Yield Enhancement ◽  
Production Test ◽  
Final Test ◽  
Critical Design ◽  
The Past ◽  
Product Engineering ◽  
Time Savings ◽  
Analysis Design

Abstract Failure isolation and debug of CMOS integrated circuits over the past several years has become increasingly difficult to perform on standard failure analysis functional testers. Due to the increase in pin counts, clock speeds, increased complexity and the large number of power supply pins on current ICS, smaller and less equipped testers are often unable to test these newer devices. To reduce the time of analysis and improve the failure isolation capabilities for failing ICS, failure isolation is now performed using the same production testers used in product development, multiprobe and final test. With these production testers, the test hardware, program and pattern sets are already available and ready for use. By using a special interface that docks the production test head to failure isolation equipment such as the emission microscope, liquid crystal station and E-Beam prober, the analyst can quickly and easily isolate the faillure on an IC. This also enables engineers in design, product engineering and the waferfab yield enhancement groups to utilize this equipment to quickly solve critical design and yield issues. Significant cycle time savings have been achieved with the migration to this method of electrical stimulation for failure isolation.

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