Layout optimisation for yield enhancement in on-chip-VLSI/WSI parallel processing

1992 ◽  
Vol 139 (1) ◽  
pp. 21
Author(s):  
P. Mazumder
Keyword(s):  
Parallel Processing ◽  
Yield Enhancement ◽  
On Chip

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals Product On-Chip Process Compensation for Low Power and Yield Enhancement

2010 ◽  
pp. 247-255
Author(s):  
Nabila Moubdi ◽  
Philippe Maurine ◽  
Robin Wilson ◽  
Nadine Azemard ◽  
Vincent Dumettier ◽  
...  
Keyword(s):  
Low Power ◽  
Yield Enhancement ◽  
On Chip

Development of a Network on Chip for Parallel Processing Systems

2010 ◽  
Author(s):  
K. Tanaka ◽  
S. Iwanami ◽  
T. Ohashi ◽  
T. Yamakawa ◽  
C. Fukunaga
Keyword(s):  
Parallel Processing ◽  
Network On Chip ◽  
On Chip

Parallel Processing of Sequential Media Algorithms on Heterogeneous Multi-Processor System-on-Chip

2009 ◽  
Vol 4 (6) ◽  
Author(s):  
Peng Zhao ◽  
Dawei Wang ◽  
Ming Yan ◽  
Sikun Li
Keyword(s):  
Parallel Processing ◽  
System On Chip ◽  
On Chip

Design and Implementation of a Low-Cost Scalar Multiplier-on-Chip for Elliptic Curve Cryptosystem

2013 ◽  
Vol 284-287 ◽  
pp. 3395-3400
Author(s):  
Wen Tzeng Huang ◽  
Ching Kuo Wang ◽  
Guo Ming Sung ◽  
Chiu Ching Tuan
Keyword(s):  
Parallel Processing ◽  
Elliptic Curve ◽  
Circuit Design ◽  
Low Cost ◽  
Scalar Multiplication ◽  
Pipeline Architecture ◽  
And Performance ◽  
On Chip ◽  
Processor Cores ◽  
Processing Architecture

In the ECC, scalar multiplication represents the core operation of the system. In recent years, the circuit architecture of triple processor cores or greater has been addressed in the domestic and international literature. A parallel processing concept is mainly used in this type of framework to accelerate circuit operation. In the present study, equation calculation and circuit design were employed to integrate the pipeline architecture and the parallel processing architecture and further propose an elliptic curve scalar multiplier for dual processor cores. In addition, a Xilinx XC5VLX110T FPGA was used to verify the accuracy and performance of circuit functions. The maximum frequency was 173 MHz, the number of LUTs was 14999 slices, and the time to accomplishing one scalar multiplication was only 8.8s. Compared to architectures described in recent reports, the architecture presented was faster and effectively reduced the square measure by 28%.

A 1Mb ROM with on chip ECC for yield enhancement

1983 ◽  
Author(s):  
T. Shinoda ◽  
Y. Ohnishi ◽  
H. Kawamoto ◽  
K. Takizawa ◽  
K. Narita
Keyword(s):  
Yield Enhancement ◽  
On Chip
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