Implementing the generalized matrix product on a systolic array parallel architecture

1997 ◽  
Author(s):  
James R. Stright
Keyword(s):  
Systolic Array ◽  
Parallel Architecture ◽  
Matrix Product ◽  
Generalized Matrix ◽  
Generalized Matrix Product

High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA

2017 ◽  
Vol 15 (05) ◽  
pp. 1750047 ◽  
Author(s):  
S. S. Divakara ◽  
Sudarshan Patilkulkarni ◽  
Cyril Prasanna Raj
Keyword(s):  
Systolic Array ◽  
High Speed ◽  
Parallel Architecture ◽  
Software Implementation ◽  
Wavelet Filter ◽  
Image Transformation ◽  
Complex Wavelet Transform ◽  
Pipelined Architecture ◽  
Array Architecture ◽  
Processing Architecture

In this paper, systolic array-based novel architecture for dual-tree complex wavelet transform (DTCWT) computation is designed and implemented on FPGA. The wavelet filter coefficients of DTCWT are quantized and rounded to nearest integer and the loss in rounding and quantization is limited to 0.5[Formula: see text]dB as compared with software implementation. The parallel architecture designed computes row elements simultaneously and pipelined architecture is designed to compute column elements. The proposed architecture is modeled using Verilog and implemented on Xilinx Virtex II FPGA. For 2D implementation, the design operates at a maximum frequency of 156[Formula: see text]MHz and consumes power less than 3[Formula: see text]W. This is the first design with systolic array architecture on FPGA for DTCWT computation operating at frequencies greater than 100[Formula: see text]MHz.

scholarly journals A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Xinyu Guo ◽  
Hong Wang ◽  
Vijay Devabhaktuni
Keyword(s):  
Systolic Array ◽  
Clock Cycle ◽  
Parallel Architecture ◽  
Second Step ◽  
Local Alignment ◽  
Alignment Algorithm ◽  
Biological Sequence ◽  
Sequence Alignment Algorithm ◽  
Field Programmable ◽  
Search Tool

A design of systolic array-based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one-clock-cycle, our design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single-clock-cycle. Further, we designed a Hits Combination Block which combines overlapping hits from systolic array into one hit. These implementations completed the first and second step of BLAST architecture and achieved significant speedup comparing with previously published architectures.

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